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For the CMOS circuit below, complete the truth table. NOTE: For a truth table question, you only get one chance to get each answer correct. Additional tries will result in a penalty each retried portion of the table.

For the CMOS circuit below, complete the truth table. NOTE: For a truth table question, you only get one chance to get each answer correct. Additional tries will result in a penalty each retried portion of the table.

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For the CMOS circuit below, complete the truth table.
NOTE: For a truth table question, you only get one chance to get each answer correct. Additional tries will result in a penalty each retried portion of the table.

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Task 4 Digital Circuits Fig. 4.1 Fig. 4.2 Given are the CMOS gates according to Fig. 4.1 und Fig. 4.2. a) For the gate from Fig. 4.1 determine the output logic values of Y for all possible input logic values A, B, and C and enter them into a truth table. For some logic states you will not be able to determine the output logic value. Denote these states with Y = Z and explain why a definite value for Y cannot be given. b) Now consider the circuit in Fig. 4.2. Determine the output logic values of Y for all possible input logic values A, B, C, and D and enter them into a truth table. c) Draw the circuit diagram of a level-sensitive D-latch and an edge-triggered master-slave Dflipflop. Given is a sequential circuit according to Fig. 4.3. The edge-triggered registers exhibit the following specifications: setup-time tsetup = 200 ps, hold-time thold = 100 ps, propagation delay tpcq = 50 ps, and contamination delay tccq = 50 ps. The maximum clock frequency is 1 GHz. Fig. 4.3 d) Determine the minimal contamination delay tcd for the combinational logic. e) Determine the maximum propagation delay tpd for the combinational logic.
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The figure below shows a transistor logic circuit constructed with two NMOS transistors and a 10 kΩ pull-up resistor. For this problem, assume that the effective resistance between drain and source is approximately 0 Ω for the ON state and an open circuit for the OFF state. 1.1 Copy this truth table to your answer sheet and fill it in. Calculate the value for Vout and indicate the state of each of the transistors (ON or OFF) for each of the following input combinations. All voltages are referenced to GND. 1.2 What logic gate does this circuit implement? 1.3 What is the power this logic circuit consumes when Vout = 0 V?

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Fill in the truth table for the circuit above. It's easy to do. When the input to an NMOS transistor is 1 , the transistor turns on. Therefore, in the circuit above, when C is a 1, the output, F, will be zero. Now you can fill that in on the truth table; whenever C is a 1, F will be 0 . You should also see that when A is 1 and B is 0, the output, F, will be 0, because both series NMOS transistors are on. The PMOS transistor are in the pull-up network. They turn on when their input is 0. If you carefully check every input case, you will see the when the pull-up network is on, the pull-down network is off, and vice-versa. That is a requirement for proper CMOS design. Use the reasoning described above to complete the entire truth table.
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