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For the CMOS inverter circuit shown below, with the given transistor parameters, determine the input voltage V1 for an output voltage of Vo = 4.8V.

For the CMOS inverter circuit shown below, with the given transistor parameters, determine the input voltage V1 for an output voltage of Vo = 4.8V.

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For the CMOS inverter circuit shown below, with the given transistor parameters, determine the input voltage V1 for an output voltage of Vo = 4.8V.

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In the dynamic logic circuit shown below, all the transistors have the minimum channel length, and their sizes (widths) are marked. The inverter at the output is a standard static CMOS inverter with a PMOS size of 2 and an NMOS size of 1 . For a unit-sized NMOS or PMOS transistor, the intrinsic capacitance at its drain or source terminal is CD, and the capacitance at its gate is CG. For unit-sized NMOS and PMOS transistors, their onresistances are RN and RP, respectively. CD = CG = 1 fF and RP = 2 RN = 2 kΩ. (a) Express y as a Boolean function of the inputs A, B, C and D in the evaluation phase (CLK = 1). (b) Find the capacitances at nodes y, a, b and c, respectively. (c) Let A = B = D = 1 and C = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase (CLK = 0). Estimate the time it takes for the voltage at y to decrease from VDD to VDD/2 in the evaluation phase. (d) Repeat (c) if nodes a, b and c are at VDD in the pre-charge phase. (e) If the inputs are C = 1 and A = B = D = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase. Considering the charge sharing effect, what is the voltage at node y in the evaluation phase? It is known VDD = 2.5 V, VTN = 0.5 V and the body effect of the transistors can be ignored.

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For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
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a. For the circuit shown below, show a clean and labeled small signal equivalent circuit and derive the expression for vo/vb, (vb is the small signal voltage at the base node) vo/vsig, Rin and Rout. (b) This is the design part. The specifications are as follows: The required gain vo/vb = −120 V/V, Ic = 1 mA. and the require voltage swing at the output is ±3 V around the DC value of the output. (Hint: Do not use the generic design rule. You should be able to find the DC voltages at the collector and emitter from the specifications). Assume Vcc = 8 V. For this design assume VA = ∞ (this makes ro = ∞), V T (Thermal Voltage) = 25 mV, VBE = 0.7 V, VCEsat = 0.3 V and β = ∞. Find the values of RC, RE, RB1, and RB2. (c) If the β = 100 instead of the design value, find the new Ic. Now assuming VA = 50 V find vo/vsig, Rout and RIN. For this part assume Rsig = 10 kΩ. Punt: If you could not answer (b), use RC = 3 kΩ, RE = 2 kΩ, RB1 = 50 kΩ, and RG2 = 30 kΩ (d) Run a transient simulation of the designed circuit in Multisim. Use the same BJT used in the lab simulation. Show the input voltage v sig and output voltage v o on the same plot. Choose vsig to be at 1 kHz and 10 mV peak sinusoidal. Compare with calculated value of the gain in part c.
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