For the following full wave rectifier, the output voltage, v3, is shown along with the voltages at the secondary of the transformer, v1 and v2. Figure P3.108(a) Is this circuit operating correctly? If the circuit is operating correctly, explain why the input and output voltages are appropriate. If the circuit is not operating correctly, explain how that is determined from the given waveforms.
![A full-wave bridge rectifier circuit is shown in Fig. 2(a) with a "floating" signal generator and grounded load resistor, which is the most common configuration of this rectifier. Its output waveform appears in Fig. 2 b. Note that the output frequency is twice the input frequency, but the time period T and angular period 2π on the horizontal axis refer to the input waveform. Following a similar development to the halfwave rectifier, the dc output voltage from the full-wave bridge rectifier is given by: Vavg = 1π∫θ1 θ2[Vmsin(θ) − 2Vd]dθ Where, the integration is over half the original waveform's period and the 2Vd term is due to the load current flowing through two diodes. The peak output voltage is vo, peak = Vm − 2Vd. The integration limits are found using Eq. 5 with the angles referred to the original input waveform. θ1 = sin−1(2Vd/Vm) and θ2 = π − θ1 However, the full-wave rectifier's conduction angle must be referred to the output waveform's period, which is half that of the input so φ = 2(θ1−θ2). (a) (b) Fig. 2. (a) Full-wave bridge rectifier circuit and (b) output waveform. Perform the following calculations for the full-wave rectifier in Fig. 2. Put your results in Table 1. a. Determine vo,peak, θ1, and θ2 for the rectifier output waveform of Fig. 2 b. b. Calculate the average (dc) value of vo(t) using Eq. 4 . c. Calculate the conduction angle φ.](https://www.doubtrix.com/uploads/editor/6776072514rhzokOtWGl.png)
![(a) Assume that the MOSFET in Figure 3.1 is operating in saturation and is characterised by a threshold voltage, VT = 1 V. Assume that the parameter, K = 1 mA/V2 where the drain-source current in the MOSFET in saturation is given by the usual expression: iDS = K2(vGS−VT)2 Calculate the output voltage, vo, for the circuit shown in Figure 3.1 when vIN = 2.5 V, Vs = 10 V, and R = 1 kΩ. The correct solution should satisfy both conditions necessary for the device to operate in saturation. Figure 2.1 [10 marks] (b) For the circuit in Figure 2.1, calculate the small signal voltage gain of the circuit, Av, at the operating point defined by the numerical values of part (a). Assume the input and output voltages include small signal components, vin and vout respectively. VIN and Vout correspond to the constant DC components of the input and output voltage from part (a). vIN = VIN +vin vOUT = VOUT +vout Av = vout vin [10 marks] (c) Determine the small signal output impedance at the terminals labelled a and b for the circuit shown in Figure 3.1 and at the operating point defined by the numerical values of part (a). [10 marks]](https://www.doubtrix.com/uploads/editor/3475428305cJOidAHSIp.jpg)
![Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1. Here are the problem parameters:The NMOS devices have gmn = 6 mA/V and rdsn = 25 kΩ. The PMOS devices have gmp = 3 mA/V and rdsp = 15 kΩ. Resistor values are R1 = 1 kΩ and R2 = 3 kΩ. a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. OL = Vout /Vin . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2 nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except Vin. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout, oL. , i. e. , the resistance seen looking in at the output node Vout. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: LG = |Vout /Vtest | For the purposes of this analysis, you should deactivate all sources in the circuit, except Vtest. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e. g. , parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain Av, CL = Vout /Vin . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av, cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine Av, cL in terms of, e. g. , Av. ol. and/or Rout, ol and/or LG (i. e. , resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av, ol and/or Rout, ol. and/or LG instead of gmn, gmp, rdsn, rdpp , R1, R2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout, CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.](https://www.doubtrix.com/uploads/editor/5672518564OTwrDIyJcJ.jpg)