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For the following logic functions: a. Design the PUN and PDN. b. Identify the input combinations that the PUN will be conducting and for each combination determine the PUN resistance, rPUN , in terms of rSDP of a single PMOS component. c. Identify the input combinations that the PDN will be conducting and for each combination determine the PDN resistance, rPDN , in terms of rDSN of a single NMOS component. d. Using kn = kp = 5 mA/V2, Vtn = |Vtp | = 1 V, and VDD = 3 V, determine rDSN and rsDP . Y = A¯⋅B⋅C¯ + D¯⋅B¯Y = A¯⋅B¯⋅C¯ + D + B¯

For the following logic functions: a. Design the PUN and PDN. b. Identify the input combinations that the PUN will be conducting and for each combination determine the PUN resistance, rPUN , in terms of rSDP of a single PMOS component. c. Identify the input combinations that the PDN will be conducting and for each combination determine the PDN resistance, rPDN , in terms of rDSN of a single NMOS component. d. Using kn = kp = 5 mA/V2, Vtn = |Vtp | = 1 V, and VDD = 3 V, determine rDSN and rsDP . Y = A¯⋅B⋅C¯ + D¯⋅B¯Y = A¯⋅B¯⋅C¯ + D + B¯

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For the following logic functions: a. Design the PUN and PDN. b. Identify the input combinations that the PUN will be conducting and for each combination determine the PUN resistance, r PUN , in terms of r SDP of a single PMOS component. c. Identify the input combinations that the PDN will be conducting and for each combination determine the PDN resistance, r PDN , in terms of r D S N of a single NMOS component. d. Using k n = k p = 5 m A / V 2 , V tn = | V tp | = 1 V , and V D D = 3 V , determine r D S N and r sDP .
Y = A ¯ ⋅ B ⋅ C ¯ + D ¯ ⋅ B ¯ Y = A ¯ ⋅ B ¯ ⋅ C ¯ + D + B ¯

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