For the pseudo NMOS circuit shown in Fig. 5, what is the output voltag

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For the pseudo NMOS circuit shown in Fig. 5, what is the output voltage and static power dissipation: a) if only one input is high? b) all four inputs are high? C) Compare analytically obtained results with SPICE simulations. Assume VDD = 2.5 V, Vtn = |Vtp| = 0.4 V.

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For the pseudo NMOS circuit shown in Fig.5, what is the output voltage and static power dissipation: a) if only one input is high? b) all four inputs are high? C) Compare analytically obtained results with SPICE simulations. Assume $V_{D D} = 2.5 V$ , $V_{t n} = | V_{t p} | = 0.4$ $V$ .