For the the SRAM cell in the figure below : a. Find the Maximum allowable W/L for the access transistor of the SRAM cell in the figure below so that in a read operation, the voltage at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.18 μm technology for which VDD = 1.8 V, Vtn = |Vtp| = 0.5 V and (W/L)n = 1.5 b. Determine the read delay Δt when (W/L)5 = 1.5. Let μnCox = 300 μA/V2. And CB = 2 pF and the sense Amplifier requires a ΔV of minimum magnitude of 0.2 V. [Hint: determine Is and recall that VQ¯ = Vt.]