For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units If you half the bias current, what happens to the small signal gain?
![For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units [Give your answer in kΩ to 4 decimal places, no units, no unit prefixes, no commas. Example: 2 kΩ → Answer Given: 2.0000 ] What is the small signal output resistance, Rout , at v0 looking back into the circuit?](https://www.doubtrix.com/uploads/editor/3153069783zzpkDyetOq.jpeg)
![For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units [Give your answer in number form to 4 decimal places, no units, no unit prefixes, no commas. Be sure to include if it is positive or negative Example: - 2 V/V -- > Answer Given: −2.0000] What is the small signal voltage gain (vo/vin) of this circuit?](https://www.doubtrix.com/uploads/editor/4297678167IJcTHgttlm.jpeg)
