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Give the truth table for the following transistor level schematic. Explain the source of "good logic 0’s i.e., GND" and "good logic 1 ’s i.e., VDD" (using the labels P1, P2, N1 and N2) at C under each of the four input conditions ( AB = 00, 01, 10, 11). A B OUT Source of Good Logic 0 at C Source of Good Logic 1 at C 0 0 0 1 1 1 1 0

Give the truth table for the following transistor level schematic. Explain the source of "good logic 0’s i.e., GND" and "good logic 1 ’s i.e., VDD" (using the labels P1, P2, N1 and N2) at C under each of the four input conditions ( AB = 00, 01, 10, 11). A B OUT Source of Good Logic 0 at C Source of Good Logic 1 at C 0 0 0 1 1 1 1 0

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Give the truth table for the following transistor level schematic. Explain the source of "good logic 0’s i.e., GND" and "good logic 1 ’s i.e., VDD" (using the labels P1, P2, N1 and N2) at C under each of the four input conditions ( AB = 00, 01, 10, 11). A B OUT Source of Good Logic 0 at C Source of Good Logic 1 at C 0 0 0 1 1 1 1 0

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