Given the nMOS inverter circuit as shown below: The W/L ratio for M1 is twice that for M2. The threshold voltage VT for both the transistors is 1 V. Find the voltage at Vx.
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Given the nMOS inverter circuit as shown below: The W/L ratio for M1 is twice that for M2. The threshold voltage VT for both the transistors is 1 V. Find the voltage at Vx.
![Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].](https://www.doubtrix.com/js/ckeditor/filemanager/connectors/php/editor/1701517361-Ahgt08pgkfy.jpeg)
![Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].](https://www.doubtrix.com/js/ckeditor/filemanager/connectors/php/editor/1701517372-Bgfiogfui.jpeg)
![[MOSFET Circuits] Consider the MOSFET circuit as shown below. R = 1kΩ, kn’ = 1 mA/V2 and Vtn = 0.3 V for both Q1 and Q2, W/L = 0.5μm/0.1μm for Q1, W/L = 1μm/0.1μm for Q2, λ = 0 and vSB = 0. (a) Calculate the voltage at the drain terminal of Q1. (b) What is the ratio of iD1 to iD2, where iD1 is the drain current for Q1 and iD2 is the drain current for Q2. Hint: This circuit is called the "current mirror" circuit, where the ratio of iD1 to iD2 is a fixed number, determined by W1, W2, L1 and L2, as long as both transistors are biased in saturation mode. (c) What is the maximum value of R2 so that Q2 remains in saturation mode?](https://www.doubtrix.com/uploads/editor/0609833589NADbRdqxAb.png)
