Given VDD = 1.2 V, CL = 100 fF, and fCLK = 1.5 GHz, KN = 100 uA/V2, an

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Given VDD = 1.2 V, CL = 100 fF, and fCLK = 1.5 GHz, KN = 100 uA/V2, and VTn = 0.5 V. (Ignore channel length modulation factor) i) Draw the transistor schematic for implementing logic function F = A+BCD using static CMOS gate. ii) Size the transistors for worst-case pull-up and pull-down with respect to the following inverter shown in the figure below.

Image text

Given

V_{D D} = 1.2 V, C_{L} = 100 f F

, and

f_{C L K} = 1.5 G H z, K_{N} = 100 u A / V^{2}

, and

V_{{T n}_{n}} = 0.5 V

. (Ignore channel length modulation factor) i) Draw the transistor schematic for implementing logic function

F = \bar{A + B C D}

using static CMOS gate. ii) Size the transistors for worst-case pull-up and pull-down with respect to the following inverter shown in the figure below.