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If Pseudo-NMOS techniques are used to build a 2-input NAND gate with W/Lp = 2.3 and W/Ln = 28.9, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 uA/V2, k'p = 60 uA/V2

If Pseudo-NMOS techniques are used to build a 2-input NAND gate with W/Lp = 2.3 and W/Ln = 28.9, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 uA/V2, k'p = 60 uA/V2

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If Pseudo-NMOS techniques are used to build a 2-input NAND gate with W/Lp = 2.3 and W/Ln = 28.9, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 uA/V2, k'p = 60 uA/V2

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