If Pseudo-NMOS techniques are used to build a 3-input NOR gate with W/Lp = 3.6 and W/Ln = 16.3, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = -0.6 V, k'n = 150 μA/V^2, k'p = 60 μA/V^2.
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