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Implement the logic function F = (A+B)C+D+E¯ in complementary CMOS logic using minimum number of transistors as one complex static gate. It is also given that input C changes the most and input E changes the least. Size the devices so the output resistance is the same as that of a CMOS inverter whose device sizing was done so that the PMOS and NMOS aspect ratio match to have the same tpHL and tpLH For the MOSFETs the device parameters kn′ = 90 μA/V2 and kpp′ = 30 μA/V2

Implement the logic function F = (A+B)C+D+E¯ in complementary CMOS logic using minimum number of transistors as one complex static gate. It is also given that input C changes the most and input E changes the least. Size the devices so the output resistance is the same as that of a CMOS inverter whose device sizing was done so that the PMOS and NMOS aspect ratio match to have the same tpHL and tpLH For the MOSFETs the device parameters kn′ = 90 μA/V2 and kpp′ = 30 μA/V2

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Implement the logic function F = ( A + B ) C + D + E ¯ in complementary CMOS logic using minimum number of transistors as one complex static gate. It is also given that input C changes the most and input E changes the least. Size the devices so the output resistance is the same as that of a CMOS inverter whose device sizing was done so that the PMOS and NMOS aspect ratio match to have the same t p H L and t p L H For the MOSFETs the device parameters k n ′ = 90 μ A / V 2 and k p p ′ = 30 μ A / V 2

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