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In a Diode Connected NMOS, if we apply voltage across the two terminals, please write the Voltage and Current relation, and plot the Voltage and Current Relation.

In a Diode Connected NMOS, if we apply voltage across the two terminals, please write the Voltage and Current relation, and plot the Voltage and Current Relation.

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In a Diode Connected NMOS, if we apply voltage across the two terminals, please write the Voltage and Current relation, and plot the Voltage and Current Relation.

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Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V

Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V
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A minimum-size inverter is fabricated in a 0.25μm technology to has (W/L)p = (W/L)n = 0.25/0.25, Vtn = −Vtp = 0.5 V, μnCox = 267 μA/V2, μpCox = 93 μA/V2. The supply voltage VDD = 2.5V. In a procedure to determine VIL: Are Qn and Qp matched? Given the Q's data above and by equating the currents flowing in Qn and Qp at VIL: a) Derive equation (1) in two variables Vin and Vout. b) Differentiate equation (1) with respect to Vin and put dVout/dVin = −1 to get equation (2) in Vin and Vout. Eliminate Vout between equations in (1) and in (2) to get a value for Vin = VIL. Determine the low noise margin NML. Derive the expression for the inverter threshold VM and determine its value using the same parameters above. Comment on the symmetry of the inverter VTC (Voltage Transfer Characteristics) around VDD/2.
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Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3 Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3

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