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In an ideal CMOS inverter, there is static power dissipation. zero extremely low very low infinite Question 2 (20 points) In a symmetrical CMOS inverter, transconductance parameter for PMOS, Kp, is not equal to the transconductance parameter for NMOS, KN. True False

In an ideal CMOS inverter, there is static power dissipation. zero extremely low very low infinite Question 2 (20 points) In a symmetrical CMOS inverter, transconductance parameter for PMOS, Kp, is not equal to the transconductance parameter for NMOS, KN. True False

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In an ideal CMOS inverter, there is static power dissipation. zero extremely low very low infinite
Question 2 (20 points) In a symmetrical CMOS inverter, transconductance parameter for PMOS, K p , is not equal to the transconductance parameter for NMOS, K N . True False

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In an ideal CMOS inverter, VOH is equal to VDD. However, the NMOS leakage may slightly reduce VOH. In this problem, we want to calculate the VOH in the presence of NMOS leakage. To measure VOH, you connect the input to the ground, where the PMOS is in linear region and the NMOS is in cut off region. However, in the presence of leakage, you can approximate that the NMOS behaves like a current source with the current of IOFF(NMOS) as shown in the circuit below. Compute VOH, if IOFF(NMOS) = 1 uA, VDD = 1.0 V, Vtp = -0.4 V, K'p = -40 mu A/V2, and (W/L)p = 2.
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Problem 3: (Short Circuit Power Consumption) For the circuit in Figure 2, assume that the input Vin is a periodic square wave signal (called "clock") of frequency 200 MHz, and has a rising transition time (from 0−100% of VDD ) of 0.2 ns and a falling transition time (from 100−0% of VDD ) of 0.2 ns. For the inverter in the figure, find the short circuit power consumption. Use the procedural hints listed below. Procedural Hints:Calculate the short circuit duration, tsc. Short circuit currents occur when both nMOS and pMOS transistors are simultaneously ON. Use the rise/fall times given. Calculate the peak short circuit currents. For simplicity assume that Ipeak_sc_LH and Ipeak_sc_HL are equal, and calculate the latter only. To calculate Ipeak_sc_HL, , assume that the short circuit current for the H-to-L transition peaks when Vin = VDD/2 and Vout = 9 VDD /10 (this is an arbitrary choice assumed for this problem alone). Now calculate the pMOS transistor current - this will be Ipeak_sc_HL. . Question: Does the nMOS current equal the pMOS current? If not, how do you account for InMOS−IpMO ? Using your results from (1) and (2), calculate the short circuit power dissipation. Note: Assume that VDD = 1.0 Volts, (W/L)p = 3.5 /0.1, and (W/L)n = 2 /0.1. Transistor properties are given by the 90 nm model parameters handout posted on the class web-site. For the current calculation, use the transistor parameters (not the equivalent resistance parameters) and ignore channel length modulation. Assume that there is an 89 fF load on Out.

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Pass Transistor Logic VDD = 2.5 V(W/L)2 = 1.5 um/0.25 um (W/L)1 = 0.5 um/0.25 um (W/L)ni = 0.5 um/0.25 um kn′ = 115 uA/V2, kp′ = −30 uA/V2 VtN = 0.43 V, VtP = −0.4 V Figure 6.12 Level restoring circuit. Consider the circuit of Figure 6.12 . Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. a. What is the logic function performed by this circuit? b. Explain why this circuit has non-zero static dissipation. c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. d. Implement the same circuit using transmission gates. e. Replace the pass-transistor network in Figure 6.12 with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A, B and C.

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