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In the circuit of Fig. P3-1, a DMM is used to measured the drain-source resistance rDS as a function of applied gate-source voltage VGS. The following data is obtained: Estimate the threshold voltage Vt and kn’W/L for this MOSFET. Figure P3-1. P2. The MOSFET from part P1 is used in the resistive load logic inverter shown in Figure P3-2. Find vOUT for vIN = 0 V and vIN = +5 V. Fig. P3-2 vGS rDS 1.0 V ∞ 1.5 3180Ω 2.0 710Ω 2.7 330Ω 4.0 180Ω

In the circuit of Fig. P3-1, a DMM is used to measured the drain-source resistance rDS as a function of applied gate-source voltage VGS. The following data is obtained: Estimate the threshold voltage Vt and kn’W/L for this MOSFET. Figure P3-1. P2. The MOSFET from part P1 is used in the resistive load logic inverter shown in Figure P3-2. Find vOUT for vIN = 0 V and vIN = +5 V. Fig. P3-2 vGS rDS 1.0 V ∞ 1.5 3180Ω 2.0 710Ω 2.7 330Ω 4.0 180Ω

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In the circuit of Fig. P3-1, a DMM is used to measured the drain-source resistance rDS as a function of applied gate-source voltage VGS. The following data is obtained: Estimate the threshold voltage Vt and kn’W/L for this MOSFET. Figure P3-1. P2. The MOSFET from part P1 is used in the resistive load logic inverter shown in Figure P3-2. Find vOUT for vIN = 0 V and vIN = +5 V. Fig. P3-2 vGS rDS 1.0 V ∞ 1.5 3180Ω 2.0 710Ω 2.7 330Ω 4.0 180Ω

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Consider the circuit configuration shown below, which is commonly used for measuring n-channel MOSFET parameters. The transistor's length and width are 1 μm. The accompanying graph plots the transistor's square root of drain current vs. gate voltage, VG. a) Estimate the threshold voltage of the n-channel MOSFET. b) When VG is between 1.5 V and 2.5 V, in what region is the device operating? Consider the p-channel MOSFET amplifier given to the right. ID = 12 kp(VSG − |Vtp|)2, VDD = 5 V, RL = 2 kΩ, kp = 1 mA/V2, Vtp = −1 V c) Derive an expression for the transistor bias point, VGQ, as a function of VDD, Ra, and Rb. d) Determine the required ratio Ra/Rb such that the MOSFET current, ID = 0.5 mA e) What is the voltage bias point of the output VoutQ? Use the value(s) from part d. Please show all steps. A_ = 0.5 VB = Saturation C = VoD(Rb/(Ra+Rb))D = Ra/Rb = 2/3 E = 1 V)

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(a) Assume that the MOSFET in Figure 3.1 is operating in saturation and is characterised by a threshold voltage, VT = 1 V. Assume that the parameter, K = 1 mA/V2 where the drain-source current in the MOSFET in saturation is given by the usual expression: iDS = K2(vGS−VT)2 Calculate the output voltage, vo, for the circuit shown in Figure 3.1 when vIN = 2.5 V, Vs = 10 V, and R = 1 kΩ. The correct solution should satisfy both conditions necessary for the device to operate in saturation. Figure 2.1 [10 marks] (b) For the circuit in Figure 2.1, calculate the small signal voltage gain of the circuit, Av, at the operating point defined by the numerical values of part (a). Assume the input and output voltages include small signal components, vin and vout respectively. VIN and Vout correspond to the constant DC components of the input and output voltage from part (a). vIN = VIN +vin vOUT = VOUT +vout Av = vout vin [10 marks] (c) Determine the small signal output impedance at the terminals labelled a and b for the circuit shown in Figure 3.1 and at the operating point defined by the numerical values of part (a). [10 marks]

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Figure P5-1 shows a common source single transistor MOSFET amplifier utilizing an N-Channel Enhancement Mode MOSFET. The term "common source" refers to the source terminal being shared by both the input circuit and the output circuit. The parameters for the MOSFET and the supply voltage are also given. Hand Analysis P1. In terms of DC bias, determine a value for VGS to set the drain current ID to 5 mA. Also determine a value for RD to set the VDS bias to 6 V. P2. In terms of small-signal parameters, determine the transconductance gm of this amplifier as well as the voltage gain, Av. P3. If vgs is a 0.1 Vpk sinewave at a frequency of 1 kHz [ie. vgs = 0.1sin(2pift)V ] determine an expression for the output voltage vOUT as a function of time. Sketch vIN and vOUT for two complete cycles, including the DC bias for each signal. Simulation P4. Simulate the circuit of Figure P5-1 to verify your hand analysis and create a plot similar to P3 as part of your prelab. Use the virtual MOSFET model in simulation with SPICE parameters VT0 = 1.8 V and KP = 120 mA/V2. (The default values of 100um for W and L will be fine since their ratio equals unity.)
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