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In the following circuits (Figs. 1 and 2), assume that all devices have |VTh|= 2V and exhibit |ID(sat)|= 2mA when |VGS |= 3V. 1. Solve for the drain current IDfor the MOSFET in Fig. (1) 2. Solve for the drain current IDfor the MOSFET in Fig. (2) NOTE!!: You can check your answers for problems 1 and 2 using KVL. The positive current ID direction for NMOS/PMOS devices is indicated by the arrow direction on the transistor

In the following circuits (Figs. 1 and 2), assume that all devices have |VTh|= 2V and exhibit |ID(sat)|= 2mA when |VGS |= 3V. 1. Solve for the drain current IDfor the MOSFET in Fig. (1) 2. Solve for the drain current IDfor the MOSFET in Fig. (2) NOTE!!: You can check your answers for problems 1 and 2 using KVL. The positive current ID direction for NMOS/PMOS devices is indicated by the arrow direction on the transistorIn the following circuits (Figs. 1 and 2), assume that all devices have |VTh|= 2V and exhibit |ID(sat)|= 2mA when |VGS |= 3V. 1. Solve for the drain current IDfor the MOSFET in Fig. (1) 2. Solve for the drain current IDfor the MOSFET in Fig. (2) NOTE!!: You can check your answers for problems 1 and 2 using KVL. The positive current ID direction for NMOS/PMOS devices is indicated by the arrow direction on the transistor

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In the following circuits (Figs. 1 and 2), assume that all devices have |VTh|= 2V and exhibit |ID(sat)|= 2mA when |VGS |= 3V. 1. Solve for the drain current IDfor the MOSFET in Fig. (1) 2. Solve for the drain current IDfor the MOSFET in Fig. (2) NOTE!!: You can check your answers for problems 1 and 2 using KVL. The positive current ID direction for NMOS/PMOS devices is indicated by the arrow direction on the transistor

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Solve for the drain current ID for the MOSFET in Fig. (1). Assume that the transistors have |VTh| = 1 V and exhibit |ID(sat)| = 2 mA when |VGS| = 3 V Solve for the drain current ID for the MOSFET in Fig. (2). Assume that the transistors have |VTh| = 1 V and exhibit |ID(sat)| = 2 mA when |VGS| = 3 V NOTE!!: You can check your answers for problems 1 and 2 using KVL. The positive current ID direction for NMOS/PMOS devices is indicated by the arrow direction on the transistor's source terminal. The VGS=|3 V| and |ID(sat)| = 2 mA given above are NOT the transistor operating voltage/current when it is connected to the four resistor circuits in Fig. (1) and Fig. (2).

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In the following circuits (Figs. 3 and 4), assume that |VTh|= 1Vand |ID(sat)|= 1mA when |VGS |= 3V. For problems 3a, 3b, 4a, and 4b, the transistors MUST have a drain current of 3mA (|ID|= 3mA). 3a. Design Fig. 3 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 3b. For Fig. 3 circuit, if R1= 10 kohm, RSS = 500 ohm, and the transistor is known to be operating in the saturation region, what is the value of R2? 4a. Design Fig. 4 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 4b. For Fig. 4 circuit, if RSS = 500 ohm, what is the largest RD value that will allow the transistor to still operate in the saturation regime? In the following circuits (Figs. 3 and 4), assume that |VTh|= 1Vand |ID(sat)|= 1mA when |VGS |= 3V. For problems 3a, 3b, 4a, and 4b, the transistors MUST have a drain current of 3mA (|ID|= 3mA). 3a. Design Fig. 3 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 3b. For Fig. 3 circuit, if R1= 10 kohm, RSS = 500 ohm, and the transistor is known to be operating in the saturation region, what is the value of R2? 4a. Design Fig. 4 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 4b. For Fig. 4 circuit, if RSS = 500 ohm, what is the largest RD value that will allow the transistor to still operate in the saturation regime?

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For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
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