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In this question, we will study the source follower cascaded by a CS stage. Neglect body effect and channel length modulation. (a) First we carry out a dc analysis on the CS stage. In the CS stage circuit shown in Figure 1, assume μnCox(W/L)1 = μpCox(W/L)2 = 1mA/V2, VTN = 0.7V, VTP = −1V, VDD = 2.5V. Calculate I1 and VOUT such that M1 operates in saturation with VGS1 = 0.8 V. What is VIN if M1 is at the edge of saturation? (b) Then we do small signal analysis on the CS stage. In the circuit shown in Figure 1, derive the small signal voltage gain Av = vout/vin. What is the maximum dc level of Vin for which M1 remains saturated? Express VIN by VDD, gate-source voltages and threshold voltages of M1 and M2. (c) To accommodate an input de level close to VDD, we further cascade it with a source follower as shown in Figure 2. Derive the small signal gain vout/vin. If VIN = VDD, what relationship between the gate-source voltages of M2 and M3 guarantees that M1 is saturated?

In this question, we will study the source follower cascaded by a CS stage. Neglect body effect and channel length modulation. (a) First we carry out a dc analysis on the CS stage. In the CS stage circuit shown in Figure 1, assume μnCox(W/L)1 = μpCox(W/L)2 = 1mA/V2, VTN = 0.7V, VTP = −1V, VDD = 2.5V. Calculate I1 and VOUT such that M1 operates in saturation with VGS1 = 0.8 V. What is VIN if M1 is at the edge of saturation? (b) Then we do small signal analysis on the CS stage. In the circuit shown in Figure 1, derive the small signal voltage gain Av = vout/vin. What is the maximum dc level of Vin for which M1 remains saturated? Express VIN by VDD, gate-source voltages and threshold voltages of M1 and M2. (c) To accommodate an input de level close to VDD, we further cascade it with a source follower as shown in Figure 2. Derive the small signal gain vout/vin. If VIN = VDD, what relationship between the gate-source voltages of M2 and M3 guarantees that M1 is saturated?

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In this question, we will study the source follower cascaded by a CS stage. Neglect body effect and channel length modulation. (a) First we carry out a dc analysis on the CS stage. In the CS stage circuit shown in Figure 1, assume μnCox(W/L)1 = μpCox(W/L)2 = 1mA/V2, VTN = 0.7V, VTP = −1V, VDD = 2.5V. Calculate I1 and VOUT such that M1 operates in saturation with VGS1 = 0.8 V. What is VIN if M1 is at the edge of saturation? (b) Then we do small signal analysis on the CS stage. In the circuit shown in Figure 1, derive the small signal voltage gain Av = vout/vin. What is the maximum dc level of Vin for which M1 remains saturated? Express VIN by VDD, gate-source voltages and threshold voltages of M1 and M2. (c) To accommodate an input de level close to VDD, we further cascade it with a source follower as shown in Figure 2. Derive the small signal gain vout/vin. If VIN = VDD, what relationship between the gate-source voltages of M2 and M3 guarantees that M1 is saturated?

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For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
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(a) Choose VB such that M1 is 300mV away from the triode region (VDS1 = VGS1-VTH1+300mV; M1 and M2 operate in Saturation region). (b) Calculate the small-signal voltage gain (VOUT/VIN). (c) Assume VB = 1.43 V, calculate the maximum output voltage swing to keep all transistors in saturation. Neglect channel length modulation. (d) Assume the maximum output swing is VOUT = 2.23 VPP, Calculate the swing at node X. In Fig. 2, assume (W/L)1 = 12 μm/0.18 μm, (W/L)2 = 24 μm/0.36 μm, ID1 = ID2 = 0.5 mA, and RD = 2 kΩ, VTH,N = 0.5 V, μnCox = 150 μA/V2, VDD = 3.3 V, λn = 0.1 V-1. Neglect body effect. Neglect channel length modulation except doing output impedance calculation.
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