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Next, consider the simple cascode current mirror shown in Figure 2 below. a) Explain the purpose of diode-connected devices M1 and M3. b) By hand, determine Vout, min such that both M2 and M4 are in saturation. How does this compare to Problem 1, part (a)? c) By hand, determine the small signal output resistance Rout. Assume M2 and M4 in saturation. Figure 2. Simple NMOS cascode current mirror for Problem 2.

Next, consider the simple cascode current mirror shown in Figure 2 below. a) Explain the purpose of diode-connected devices M1 and M3. b) By hand, determine Vout, min such that both M2 and M4 are in saturation. How does this compare to Problem 1, part (a)? c) By hand, determine the small signal output resistance Rout. Assume M2 and M4 in saturation. Figure 2. Simple NMOS cascode current mirror for Problem 2.

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  1. Next, consider the simple cascode current mirror shown in Figure 2 below. Figure 2. Simple NMOS cascode current mirror for Problem 2. a) Explain the purpose of diode-connected devices M1 and M3. b) By hand, determine Vout,min such that both M2 and M4 are in saturation. How does this compare to Problem 1, part (a)? c) By hand, determine the small signal output resistance Rout. Assume M2 and M4 in saturation.

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Now, consider the high-swing cascode current mirror shown in Figure 3 below. Figure 3. High-swing NMOS cascode current mirror for Problem 3. a) By hand, determine Mx2 length Lx2 such that VDS2 is 25% larger than VON2; i. e. , design Lx⁡2 such that VDS2 = (1+α)VON2 = 1.25VON2, with α = 0.25. b) By hand, determine Vout, min such that M2 and M4 are in saturation. Assume Lx2 and VDS2 as in part (a). c) By hand, determine the small signal output resistance. Assume M2 and M4 in saturation.

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Consider the simple current mirror shown in Figure 1 below. Figure 1. Simple NMOS current mirror for Problem 1. a) By hand, determine Vout, min such that M2 is in saturation. b) By hand, determine the small signal output resistance Rout. Assume M2 in saturation. c) Sketch Iout vs. Vout over the range Vout, min = Vout ≤ VDD . d) In SPICE, verify your result of part (a), and briefly discuss any agreement/disagreement between the hand analysis and simulation results. e) In SPICE, verify your result of part (b), and briefly discuss any agreement/disagreement between the hand analysis and simulation results.

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For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
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