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P R O B LEM II. 6 a) Express F¯ in a simplified sum-of-products form given that F = AB¯+CD¯. b) Implement the logic function F = AB¯+CD¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds VIL = VOL = VL and VIH = VOH = VH, respectively. Assume the supply voltage is VS, and that the on-state resistance of the NMOS transistors is RON. Determine the lowest value of the pull-up resistor RPU for which the circuit will obey the static discipline in terms of RON, VS, VL, and VH; not all variables need appear in your answer. c) Implement the logic function F = AB¯+CD¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a). ) d) Suppose that the NMOS and CMOS circuits above drive a capacitance CL. Assume that the on-state resistance of both the PMOS and NMOS transistors is RON. For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to VH. Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1, C = 0, and D = 1, and that a 0−V to 5−V square-wave signal is applied to the input A. Assume the square wave cycle time is T, and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance CL load.

P R O B LEM II. 6 a) Express F¯ in a simplified sum-of-products form given that F = AB¯+CD¯. b) Implement the logic function F = AB¯+CD¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds VIL = VOL = VL and VIH = VOH = VH, respectively. Assume the supply voltage is VS, and that the on-state resistance of the NMOS transistors is RON. Determine the lowest value of the pull-up resistor RPU for which the circuit will obey the static discipline in terms of RON, VS, VL, and VH; not all variables need appear in your answer. c) Implement the logic function F = AB¯+CD¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a). ) d) Suppose that the NMOS and CMOS circuits above drive a capacitance CL. Assume that the on-state resistance of both the PMOS and NMOS transistors is RON. For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to VH. Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1, C = 0, and D = 1, and that a 0−V to 5−V square-wave signal is applied to the input A. Assume the square wave cycle time is T, and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance CL load.

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P R O B LEM II. 6 a) Express F ¯ in a simplified sum-of-products form given that F = A B ¯ + C D ¯ . b) Implement the logic function F = A B ¯ + C D ¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds V I L = V O L = V L and V I H = V O H = V H , respectively. Assume the supply voltage is V S , and that the on-state resistance of the NMOS transistors is R O N . Determine the lowest value of the pull-up resistor R P U for which the circuit will obey the static discipline in terms of R O N , V S , V L , and V H ; not all variables need appear in your answer. c) Implement the logic function F = A B ¯ + C D ¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a).) d) Suppose that the NMOS and CMOS circuits above drive a capacitance C L . Assume that the on-state resistance of both the PMOS and NMOS transistors is R O N . For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to V H . Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1 , C = 0 , and D = 1 , and that a 0 − V to 5 − V square-wave signal is applied to the input A . Assume the square wave cycle time is T , and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance C L load.

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