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Parallel Connection of MOSFETs For an NMOS in saturation, IDS = 1/2Kn(Vgs - VTN)2. Imagine connecting two same NMOS in parallel (connect the gates, drains, and sources together), as shown in Figure 1. How would the IDS change compare to the IDS of a single NMOS given the same VD, VG, and VS [RP1]? Which parameter in the IDS equation (other than IDS ) is effectively changed by the parallel NMOS connection [RP1]? How would that parameter and IDS change if n NMOS are connected in parallel [RP1]? Figure 1: Parallel-connected NMOS Inverter

Parallel Connection of MOSFETs For an NMOS in saturation, IDS = 1/2Kn(Vgs - VTN)2. Imagine connecting two same NMOS in parallel (connect the gates, drains, and sources together), as shown in Figure 1. How would the IDS change compare to the IDS of a single NMOS given the same VD, VG, and VS [RP1]? Which parameter in the IDS equation (other than IDS ) is effectively changed by the parallel NMOS connection [RP1]? How would that parameter and IDS change if n NMOS are connected in parallel [RP1]? Figure 1: Parallel-connected NMOS Inverter

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Parallel Connection of MOSFETs For an NMOS in saturation, IDS = 1/2Kn(Vgs - VTN)2. Imagine connecting two same NMOS in parallel (connect the gates, drains, and sources together), as shown in Figure 1. How would the IDS change compare to the IDS of a single NMOS given the same VD, VG, and VS [RP1]? Which parameter in the IDS equation (other than IDS ) is effectively changed by the parallel NMOS connection [RP1]? How would that parameter and IDS change if n NMOS are connected in parallel [RP1]? Figure 1: Parallel-connected NMOS Inverter

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For the circuit shown below, assume node "Out" was initially at 0 V and is being charged by the PMOS shown in the figure. (Assume the width of transistor is W and threshold voltage is VT, also all the parasitic capacitances associated with the transistor are negligible. ) a) (3 Points) Derive the expression for the total energy supplied by the voltage source VDD during the charging process. b) (2 Points) How would the total energy supplied by the voltage source VDD change if the transistor VT is increased by 25% ? c) (2 Points) How would the total energy supplied by the voltage source VDD change if the overdrive voltage i. e. (VSG-|VT|) is increased by 25% by pulling the gate terminal to a negative voltage? d) (2 Points) How would the energy supplied by the voltage source VDD change if the value of VDD is increased by 25% ? e) (3 Points) Derive the expression for the total energy supplied by the voltage source VDD if the PMOS is replaced by NMOS (and the gate of NMOS is connected to VDD). Assume zero current through the NMOS in cut-off region.

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Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V

Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V
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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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