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Please list two defects that can be found in a silicon crystal and draw a diagram to show how they look like in the crystal. Looking at the layout of a CMOS Inverter below, please answer the following questions considering that the process is 180 nm. What is the length of the PMOS and NMOS channels in nm? What is the width of the PMOS and NMOS channels in nm? What is the surface area PMOS and NMOS channels in nm^2?

Please list two defects that can be found in a silicon crystal and draw a diagram to show how they look like in the crystal. Looking at the layout of a CMOS Inverter below, please answer the following questions considering that the process is 180 nm. What is the length of the PMOS and NMOS channels in nm? What is the width of the PMOS and NMOS channels in nm? What is the surface area PMOS and NMOS channels in nm^2?

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Please list two defects that can be found in a silicon crystal and draw a diagram to show how they look like in the crystal. Looking at the layout of a CMOS Inverter below, please answer the following questions considering that the process is 180 nm. What is the length of the PMOS and NMOS channels in nm? What is the width of the PMOS and NMOS channels in nm? What is the surface area PMOS and NMOS channels in nm^2?

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Referring to the figure below, a CMOS gate is shown on the left and the number on each transistor indicates the width of that transistor. We would like to match the worst case delay of the CMOS gate to the inverter delay. Determine the sizes of PMOS and NMOS transistor on the Inverter gate. In the answers, first number shows the PMOS width and the second number shows the NMOS width of the inverter

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Vdd is 5V. The bias current of this circuit is 100μA. The load capacitance (CL) is 5pF. Va (the voltage at the gate of the PMOS devices) is 4.2V. The PMOS current mirror is 1:1. Assume everything is in the saturation region. Include proper units for full credit and show your work. Unless otherwise specified and if appropriate, give an equation and a number answer. For the circuit shown above, answer the following questions: (i) What is the width of device 2? (Ignore channel length modulation (λ) ). (10pts) (ii) What is the width of device 1? (Again, ignore channel length modulation (λ)) (8pts) (iii) What is the small signal gain in terms of gmx (transconductance) and gox (output conductance) where x is 1 or 2, the device number? The output transconductance of PMOS 3 can be neglected. Be sure to draw the small signal model for full credit. (8pts) (iv) (Extra Credit) What is the value of the small signal gain? (4pts)Vdd is 5V. The bias current of this circuit is 100μA. The load capacitance (CL) is 5pF. Va (the voltage at the gate of the PMOS devices) is 4.2V. The PMOS current mirror is 1:1. Assume everything is in the saturation region. Include proper units for full credit and show your work. Unless otherwise specified and if appropriate, give an equation and a number answer. For the circuit shown above, answer the following questions: (i) What is the width of device 2? (Ignore channel length modulation (λ) ). (10pts) (ii) What is the width of device 1? (Again, ignore channel length modulation (λ)) (8pts) (iii) What is the small signal gain in terms of gmx (transconductance) and gox (output conductance) where x is 1 or 2, the device number? The output transconductance of PMOS 3 can be neglected. Be sure to draw the small signal model for full credit. (8pts) (iv) (Extra Credit) What is the value of the small signal gain? (4pts)
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Part 2: Analysis of a CMOS Inverter's Dynamic Behavior Objective: Perform hand calculations of switching delays through a CMOS inverter. Consider a CMOS inverter such as the one shown in Figure 2. The delay times, trise and tsunv , will be determined by the current-driving capacities of the PMOS and NMOS transistors, respectively, as well as the magnitude of the load capacitance CL. Figure 2. CMOS Inverter The rise time trice for a CMOS inverter can be calculated as: tnse = CLΔV IDAvg , where IDP wg is the average of the PMOS currents at the 10% point of the low-to-high transition (Vout = Vtow ) and at the 90% point (Voor = Vsow ). Likewise, the fall time tfall for a CMOS inverter can be calculated as: tsanl = CLΔV IDavg , where ID timg is the average of the NMOS currents at the 90% of the high-to-low transition (Vout = VSop ) and at the 10% point (Vous = V10%). ⇒ Calculate the expected rise and fall times, trise and tfall . Use LCM equations with a load capacitance value of 25 pF. Use VT0 = 0.4 V, kn′ = 432 μA/V2, |2ϕϝ| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, WN = 2 μm, and LN = 100 nm for the NMOS device. Use Vpv = −0.4 V, kp′ = 108 μA/V2, |2ϕF| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, Wp = 8 μm, and Lp = 100 nm for the PMOS device.

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