Question

Notify Me Bookmark

problem 1 Design the inverter (determine the W/L of each device) in Fig. 1 to have a self-bias voltage of 0.9 V and a quiescent current of 108 μA when self-biased. Ignore λ for operating point calculations. What is the dc gain of this inverter? (Use this inverter for the rest of the problems). For the following problems, use the data below: μnCox = 300 μA/V2, μpCox = 75 μA/V2, VTn = VTp = 0.6 V; λp = λn = 0.1 /V Problem 1 Figure 1: Circuit for

problem 1 Design the inverter (determine the W/L of each device) in Fig. 1 to have a self-bias voltage of 0.9 V and a quiescent current of 108 μA when self-biased. Ignore λ for operating point calculations. What is the dc gain of this inverter? (Use this inverter for the rest of the problems). For the following problems, use the data below: μnCox = 300 μA/V2, μpCox = 75 μA/V2, VTn = VTp = 0.6 V; λp = λn = 0.1 /V Problem 1 Figure 1: Circuit for

Image text
For the following problems, use the data below: μ n C o x = 300 μ A / V 2 , μ p C o x = 75 μ A / V 2 , V T n = V T p = 0.6 V ; λ p = λ n = 0.1 / V
Problem 1 Figure 1: Circuit for problem 1 Design the inverter (determine the W/L of each device) in Fig. 1 to have a self-bias voltage of 0.9 V and a quiescent current of 108 μ A when self-biased. Ignore λ for operating point calculations. What is the dc gain of this inverter? (Use this inverter for the rest of the problems).

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

For all circuits, do not consider channel length modulation for calculating bias points. Unless otherwise specified, channel length modulation effect needs to be considered for small-signal analysis. All answers should be given to the second decimal place. Circuit and device parameters are: Vdd = 5 V;VTn = VTp = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; Lmin = 1 μm Figure 1 (for problems 1-3) Figure 2 (for problems 5-9) Figure 1: Transistor M1 has (W/L) = (160 μm/2 μm) and a bias current Iout = 2 mA. We desire M1 to be in saturation. You should assume λn = 0 for problems (1)-(3). Determine the ratio R1 /R2 required. 1 point Let VTn increase by 10% to 1.1 V. What is the new value of Iout in mA ? 1 point Let μnCox increase by 10% to 55 μA/V2. What is the new value of Iout in mA ? 1 point Figure 2: The circuit has Iref = 2 mA and Vp = 4 V. Transistors M1, M2 and M3 have (W/L) = (80 μm/1 μm). Determine the value of vx. (in volts) 1 point Determine the minimum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine the maximum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine Vb (in volts) such that vX = VY. 1 point determine the output resistance of this circuit ∂Vp/∂Iout in MΩ. 1 point Description for questions 9-10: An NMOS device with ID = 1 mA must operate in saturation with drain-source voltages as low as 0.5 V. The minimum required small-signal output impedance is 400 kQ. {Hint: You need to use the relations: rout = 1 /(λ⋅ID); λ⋅L = constant; and expression for VDS, sat = VGS−VT} Determine the length of the device in μm. 1 point Determine the width of the device in μm. 1 point

Solution
0 0

For all circuits, do not consider channel length modulation for calculating bias points. Unless otherwise specified, channel length modulation effect needs to be considered for small-signal analysis. All answers should be given to the second decimal place. Circuit and device parameters are: Vdd = 5 V; VTnn = VTp = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; Lmin = 1 μm Figure 1 (for problems 1-3) Figure 2 (for problems 5-9) Figure 1: Transistor M1 has (W/L) = (160 μm/2 μm) and a bias current Iout = 2 mA. We desire M1 to be in saturation. You should assume λn = 0 for problems (1)-(3). Determine the ratio R1 /R2 required. 1 point Let VTn increase by 10% to 1.1 V. What is the new value of Iout in mA ? 1 point Let μnCox increase by 10% to 55 μA/V2. What is the new value of Iout in mA ? 1 point Figure 2: The circuit has Iref = 2 mA and VP = 4 V. Transistors M1, M2 and M3 have (W/L) = (80 μm/1 μm). Determine the value of vx. (in volts) 1 point Determine the minimum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine the maximum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine Vb (in volts) such that VX = VY. 1 point determine the output resistance of this circuit ∂Vp/Iout in MQ. 1 point Description for questions 9-10: An NMOS device with ID = 1 mA must operate in saturation with drain-source voltages as low as 0.5 V. The minimum required small-signal output impedance is 400 kΩ. {Hint: You need to use the relations: rout = 1 /(λ⋅ID); λ⋅L = constant; and expression for VDS, sat = VGS−VT }Determine the length of the device in μm. 1 point Determine the width of the device in μm. 1 point

Solution
0 0

Cascode Stage. Design a Cascode amplifier shown in figure below to achieve a gain of 1600. Assume VDD = 1 V, Vth = 0.3 V, λn = 0.2 V−1, γ = 0, μnCox = 100 μA/V2, I1 = 1 mA, gmro ≫ 1. a) Find bias point (VGS−Vth of transistors) to achieve the target gain such that we achieve maximum swing at Vout. b) Find W/L for each transistor. c) Calculate optimal Vb and VIN DC bias to maximize output swing. What is this maximum/minimum voltage levels at the output? What is the maximum swing? d) Notice you must generate a specific Vb externally to maximize the swing. If a lazy designer decides to connect Vb to VDD instead, what would be the swing in this case? e) To realize the current source load, we will use a PMOS active load. For PMOS, use the same parameters with λp = 0.2 V−1, μpCox = 50 μA/V2. Assume the bias current will remain at 1mA, find the new gain value. What would be the W/L for PMOS if we want to have a VOD(VGS−Vth) of 0.1V for this device. f) Repeat part (e) for a PMOS load with 2L gate length. g) It seems like making the PMOS load very large (large W) is beneficial to reduce VOD and consequently improving the voltage swing. What do you think is the drawback?
Solution
0 0