Question

Notify Me Bookmark

Problem 2 (2 pts) - nFETs Given the circuit on the right, determine the mode of operation (saturation or triode) and find the DC value of IOUT. M1 and M2 have identical fabrication parameters. a) Solve using above threshold equations. Ignore the Early and body effects b) Solve using subthreshold equations. Ignore the Early effect.

Problem 2 (2 pts) - nFETs Given the circuit on the right, determine the mode of operation (saturation or triode) and find the DC value of IOUT. M1 and M2 have identical fabrication parameters. a) Solve using above threshold equations. Ignore the Early and body effects b) Solve using subthreshold equations. Ignore the Early effect.

Image text
Problem 2 (2 pts) - nFETs Given the circuit on the right, determine the mode of operation (saturation or triode) and find the DC value of I OUT . M1 and M2 have identical fabrication parameters. a) Solve using above threshold equations. Ignore the Early and body effects b) Solve using subthreshold equations. Ignore the Early effect.

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
Solution
0 0

Consider the circuit shown in Figure 1; note that the numerical value of Vbias is not needed for this problem. Figure 1. Circuit for Problem 1. Here, current source Ibias = 13mA and NMOS devices M1 and M2 have the following properties: • W1 = W2 = 13µm, L1 = L2 = 1µm, kn’ = 500µA/V2 , and VT = 1 V. • The body effect and channel-length modulation effect for devices M1 and M2 should be neglected for this problem. a) If VDD = 5V, determine the numerical value of output current Iout. . Show your work and include appropriate units with your numerical answer. b) If VDD = 5V, determine the numerical value of node voltage Vx. Show your work and include appropriate units with your numerical answer. c) Determine VDDmin, the minimum numerical value of VDD which ensures that device M2 is in saturation. Show your work and include appropriate units with your numerical answer.
Solution
0 0

Pass transistor logic (25 pts) Consider the circuit shown in Fig. 1. Assume the inverter has balanced pull-up and pull-down strength. Neglect body effect, short channel effects and parasitic capacitance. VDD = 2.5 V. Assume all transistors in this question have the same size and W = 0.5 um, L = 0.25 um. Use the following parameters. a) (5) What is the logic function implemented by this circuit? b) (5) Identify the input pattern that will cause non-zero static power dissipation (when subthreshold leakage is ignored) for the inverter when inputs A and B are stable. Explain the cause of this static power consumption. c) (8) Compute the static power consumption for the input pattern identified in part b). Ignore subthreshold leakage. c) (7) Show two possible solutions each with 1 additional transistor to avoid static power consumption. Fig. 1

Solution
0 0