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[ Problem 2] (5+5+10+10) For the following function f = x¯2 + x1x¯3 + x1x2x4 (a) Optimize the gate level design by using only 2-input NAND gates. Then, count total number of transistors. (b) Design CMOS circuit that minimizes the number of transistors. Then compare the number of transistors and its critical path delay with that of circuit in (a). (c) Optimize the design using FPGA utilizing 2-input LUT's. How many cells are used? (d) Implement it using 3-to-1 multiplexers only. It needs to select optimized one after investigating all possible implementations.

[ Problem 2] (5+5+10+10) For the following function f = x¯2 + x1x¯3 + x1x2x4 (a) Optimize the gate level design by using only 2-input NAND gates. Then, count total number of transistors. (b) Design CMOS circuit that minimizes the number of transistors. Then compare the number of transistors and its critical path delay with that of circuit in (a). (c) Optimize the design using FPGA utilizing 2-input LUT's. How many cells are used? (d) Implement it using 3-to-1 multiplexers only. It needs to select optimized one after investigating all possible implementations.

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[ Problem 2] ( 5 + 5 + 10 + 10 ) For the following function
f = x ¯ 2 + x 1 x ¯ 3 + x 1 x 2 x 4
(a) Optimize the gate level design by using only 2-input NAND gates. Then, count total number of transistors. (b) Design CMOS circuit that minimizes the number of transistors. Then compare the number of transistors and its critical path delay with that of circuit in (a). (c) Optimize the design using FPGA utilizing 2-input LUT's. How many cells are used? (d) Implement it using 3-to-1 multiplexers only. It needs to select optimized one after investigating all possible implementations.

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