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Problem 3: Consider the following circuit which shows a pass-gate logic network. (a) Determine the truth table for the circuit. What logic function does it implement? (b) Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve an output node (OUT) voltage, VOL = 0.2 V. (VTHP = VTHN = 0.5 V ) Assume VOL is small enough so that higher order terms of VOL can be neglected in the IDs expression of NMOS transistors. Also, assume μn/μp = 2. (c) What will be problem(s) if the PMOS is removed?

Problem 3: Consider the following circuit which shows a pass-gate logic network. (a) Determine the truth table for the circuit. What logic function does it implement? (b) Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve an output node (OUT) voltage, VOL = 0.2 V. (VTHP = VTHN = 0.5 V ) Assume VOL is small enough so that higher order terms of VOL can be neglected in the IDs expression of NMOS transistors. Also, assume μn/μp = 2. (c) What will be problem(s) if the PMOS is removed?

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Problem 3: Consider the following circuit which shows a pass-gate logic network. (a) Determine the truth table for the circuit. What logic function does it implement? (b) Assuming 0 and 2.5 V inputs, size the P M O S transistor to achieve an output node (OUT) voltage, V O L = 0.2 V . ( V T H P = V T H N = 0.5 V ) Assume V O L is small enough so that higher order terms of V O L can be neglected in the I Ds expression of NMOS transistors. Also, assume μ n / μ p = 2 . (c) What will be problem(s) if the PMOS is removed?

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