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Problem 6: A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0→1. If VDD = 2 V, and the change in the output is ΔVout = −1 V and ∣ΔVout ∣ > VTn, calculate the ratio of the capacitances Ca/CL.

Problem 6: A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0→1. If VDD = 2 V, and the change in the output is ΔVout = −1 V and ∣ΔVout ∣ > VTn, calculate the ratio of the capacitances Ca/CL.

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Problem 6: A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0→1. If VDD = 2 V, and the change in the output is ΔVout = −1 V and ∣ΔVout ∣ > VTn, calculate the ratio of the capacitances Ca/CL.

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A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0->1. If VDD = 2 V, and the change in the output is Vout = 1 V, calculate the ratio of the capacitances Ca/CL.
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Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?

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In the dynamic logic circuit shown below, all the transistors have the minimum channel length, and their sizes (widths) are marked. The inverter at the output is a standard static CMOS inverter with a PMOS size of 2 and an NMOS size of 1 . For a unit-sized NMOS or PMOS transistor, the intrinsic capacitance at its drain or source terminal is CD, and the capacitance at its gate is CG. For unit-sized NMOS and PMOS transistors, their onresistances are RN and RP, respectively. CD = CG = 1 fF and RP = 2 RN = 2 kΩ. (a) Express y as a Boolean function of the inputs A, B, C and D in the evaluation phase (CLK = 1). (b) Find the capacitances at nodes y, a, b and c, respectively. (c) Let A = B = D = 1 and C = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase (CLK = 0). Estimate the time it takes for the voltage at y to decrease from VDD to VDD/2 in the evaluation phase. (d) Repeat (c) if nodes a, b and c are at VDD in the pre-charge phase. (e) If the inputs are C = 1 and A = B = D = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase. Considering the charge sharing effect, what is the voltage at node y in the evaluation phase? It is known VDD = 2.5 V, VTN = 0.5 V and the body effect of the transistors can be ignored.

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