Problem 7: Consider the CMOS SRAM cell and data lines as shown, biased

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Problem 7: Consider the CMOS SRAM cell and data lines as shown, biased at VDD = 2.5 V. Assume transistor parameters kn′ = 80 μA/V2, V tn = 0.4 V, kp′ = 35 μA/V2, Vtp = −0.4 V, W/L = 2(MN1 and MN2), W/L = 4(MP1 and MP2), and W/L = 1 (all other transistors). Assume initially that Q = 0 and Q¯ = 1. Assume the row is selected with X = 2.5 V and assume the data lines, through a write cycle, are D¯ = 0 and D = 2.5 V. Determine the values of Q¯ and Q just after the row select has been applied.

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Problem 7: Consider the CMOS SRAM cell and data lines as shown, biased at

V_{D D} = 2.5 V

. Assume transistor parameters

k_{n}^{'} = 80 μ A / V^{2}, V

tn

= 0.4 V

,

k_{p}^{'} = 35 μ A / V^{2}, V t p = - 0.4 V, W / L = 2 (M_{N 1}

and

M_{N 2})

,

W / L = 4 (M_{P 1}

and

M_{P 2})

, and

W / L = 1

(all other transistors). Assume initially that

Q = 0

and

\bar{Q} = 1

. Assume the row is selected with

X = 2.5 V

and assume the data lines, through a write cycle, are

\bar{D} = 0

and

D = 2.5 V

. Determine the values of

\bar{Q}

and

Q

just after the row select has been applied.

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