Q-3: What is the propagation delay for a falling edge in pico sec for

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Q-3: What is the propagation delay for a falling edge in pico sec for an inverter in a 0.18 μm CMOS process if the total capacitance on the output of this inverter is 75.6 fF? Use: W/Lp = 5.8, W/Ln = 16.8, VDD = 1.7 V, VTN = 0.5 V, VTP = −0.5 V, kn = 190 μA/V∧2, kp′ = 90 μA/V^2.

Q-3: What is the propagation delay for a falling edge in pico sec for an inverter in a 0.18 μm CMOS process if the total capacitance on the output of this inverter is 75.6 fF? Use: W/Lp = 5.8, W/Ln = 16.8, VDD = 1.7 V, VTN = 0.5 V, VTP = −0.5 V, kn = 190 μA/V∧2, kp′ = 90 μA/V^2.

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Q-3: What is the propagation delay for a falling edge in pico sec for an inverter in a

0.18 μ m

CMOS process if the total capacitance on the output of this inverter is

75.6 f F ?

Use:

W / L_{p} = 5.8, W / L_{n} = 16.8, V_{D D} = 1.7 V, V_{T N} = 0.5 V, V_{T P} = - 0.5 V, k_{n} =

190 μ A / V^{\land} 2, k_{p}^{'} = 90 μ A / V^{\land} 2

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