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Q2. (50%) From the study of logical effort we learned the fastest circuit is achieved whenever the stage effort is around 4. The following circuit is designed with this in mind by making the stage effort gihi on the lowest critical path all 4. Note there is a compound gate AOI22 in the 2 nd stage. In each gate, the total capacitance seen by one pin is denoted P#N# where the hash signs denote the PMOS and NMOS sizes, respectively, and are all integer values. Fill in all the missing P#N#. Then, compute the normalized delay through the network.

Q2. (50%) From the study of logical effort we learned the fastest circuit is achieved whenever the stage effort is around 4. The following circuit is designed with this in mind by making the stage effort gihi on the lowest critical path all 4. Note there is a compound gate AOI22 in the 2 nd stage. In each gate, the total capacitance seen by one pin is denoted P#N# where the hash signs denote the PMOS and NMOS sizes, respectively, and are all integer values. Fill in all the missing P#N#. Then, compute the normalized delay through the network.

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Q2. (50%) From the study of logical effort we learned the fastest circuit is achieved whenever the stage effort is around 4. The following circuit is designed with this in mind by making the stage effort g i h i on the lowest critical path all 4. Note there is a compound gate AOI22 in the 2nd stage. In each gate, the total capacitance seen by one pin is denoted P#N# where the hash signs denote the PMOS and NMOS sizes, respectively, and are all integer values. Fill in all the missing P#N#. Then, compute the normalized delay through the network.

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