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Q2. For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 pull-down transistor ratios are 100/5 VT0 = 1.0 V γ = 0.4 V1/2 |2ϕF| = 0.6 V (a) Identify the worst case input combination(s) for VOL. (b) Calculate the worst case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD∗ ) Fig. P7.5

Q2. For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 pull-down transistor ratios are 100/5 VT0 = 1.0 V γ = 0.4 V1/2 |2ϕF| = 0.6 V (a) Identify the worst case input combination(s) for VOL. (b) Calculate the worst case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD∗ ) Fig. P7.5

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Q2. For the gate shown in Fig. P7.5,
  • Pull-up transistor ratio is 5/5
  • pull-down transistor ratios are 100/5
  • V To = 1.0 V
  • γ = 0.4 V 1 / 2
  • | 2 ϕ F | = 0.6 V (a) Identify the worst case input combination(s) for V O L . (b) Calculate the worst case value of V O L . (Assume that all pull-down transistors have the same body bias and initially, that V O L ≈ 5 % V D D ∗ ) Fig. P7.5

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7.5 For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 Pull-down transistor ratios are 100/5 VTn = 0.53 V VTp = −0.51 V γ = 0.574 V1 /2 |2ΦF| = 1.020 V EC,pLp = 1.8 V a. Identify the worst-case input combination(s) for VOL. b. Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD. ) Figure P7.5

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Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
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Two CMOS inverters are connected together as shown below (Fig. 2.1). If it is needed in calculations, please use the following assumed data: gate oxide thickness tox = 7.6 nm for silicon dioxide (SiO2); built-in voltage Vbi = 0.7 V; zero-bias bottom-area junction capacitance (normalised) Cj0An = 1.10×10-4 F/m2; zero-bias sidewall capacitance ( normalised) Cj0swn = 2.19×10-11 F/m; state your assumption clearly if other additional data are needed. Sizes of M1 to M4 : (W/L)n = 0.4μm/0.2μm (W/L)p = 1.0μm/0.2μm (a). With the input waveform shown in Fig. 2.1, at time t1, what are the expected operation modes of the two n-type MOSFETs respectively? Assume that the inverters are fast enough to respond to the given input waveform. (5 marks) (b). Determine the dominant drain capacitance of M2 at time t1. Assume the worst case of the sidewall capacitance contributed from four sides. (10 marks) (c). Determine the dominant gate capacitance of M3 at time t1. (Hint: the bulk terminal of each of the MPSFET is connected to either ground or VDD ). ( 6 marks) (d). Draw a sketch comparing the output waveform with the input signal, taking into account the qualitative effects of capacitance within the MOS transistors. (4 marks)
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