Q4. Consider the CMOS diagram of the logic gate X given in Figure Q4: Figure Q4 i. Determine the logic expression of output F. [6 marks] ii. Hence derive the truth table for the logic gate X. [8 marks] Q5. Consider the CMOS diagram of the logic gate X given in Figure Q4. Derive [10 marks] the truth table for the logic gate X, by showing clearly the status of each transistor.
![Q4. Consider the CMOS diagram of the logic gate X given in Figure Q4: Figure Q4 i. Determine the logic expression of output F. [6 marks] ii. Hence derive the truth table for the logic gate X. [8 marks] Q5. Consider the CMOS diagram of the logic gate X given in Figure Q4. Derive [10 marks] the truth table for the logic gate X, by showing clearly the status of each transistor.](https://www.doubtrix.com/uploads/editor/2909203008gFIXTEehjX.png)
![The circuit shown in Figure 4 is a logic function ‘F’ implemented using NMOS transistors with the following parameters: (Given: Vt = 1V and K = 0.5 mA/V2 , RL = 20 kΩ, VDD = 10 V ); If the logic levels for the inputs ‘C & D’ are given as 10 V and 0 V for logic ‘1’ and ‘0’ respectively 1. Derive the truth table for function ‘F’ indicating the transistors’ mode of operation. (Fill in the table below) 2. Verify the mode of operation for the transistors at every row in the truth table 3. State the equivalent logic gate of ‘F’ Figure 4 Logic Function ‘F’ using NMOS Transistor Input ‘C’ logic Value Input ‘D’ logic Value M1 mode M2 mode ‘F’ Logic Value (‘1’ or ‘0’) ‘F’ Voltage Value [V]](https://www.doubtrix.com/uploads/editor/2502578211LsGYxXRBZE.jpg)
![The circuit shown in Figure 5-1 is a CMOS logic gate of some type. NOTE: Alternative symbols! a) Fill in the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] If 0 V represents a logic low, and +5 V represents a logic high, what is the logic gate function of this circuit? [2] c) Determine the output resistance ROUT of the CMOS gate of Figure 5-1 for each combination of inputs. [8] NOTE: ROUT is the Thevenin Resistance of the Gate. It is the total resistance connected between VDD and the output OR between the output and GROUND, depending on the state of the MOSFET switches. GIVEN : rDSn = 190 ohm and rDSp = 350 ohm d) If this gate exhibits a worst-case Low-to-High (tpLH) propagation delay of 60nsec when driving a given capacitive load, what would you expect the worst-case High-to-Low (tpHL) propagation delay to be?](https://www.doubtrix.com/js/ckeditor/filemanager/connectors/php/editor/1696166621-A78cbckcnnk.png)
![The circuit shown in Figure 5-1 is a CMOS logic gate of some type. NOTE: Alternative symbols! a) Fill in the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] If 0 V represents a logic low, and +5 V represents a logic high, what is the logic gate function of this circuit? [2] c) Determine the output resistance ROUT of the CMOS gate of Figure 5-1 for each combination of inputs. [8] NOTE: ROUT is the Thevenin Resistance of the Gate. It is the total resistance connected between VDD and the output OR between the output and GROUND, depending on the state of the MOSFET switches. GIVEN : rDSn = 190 ohm and rDSp = 350 ohm d) If this gate exhibits a worst-case Low-to-High (tpLH) propagation delay of 60nsec when driving a given capacitive load, what would you expect the worst-case High-to-Low (tpHL) propagation delay to be?](https://www.doubtrix.com/js/ckeditor/filemanager/connectors/php/editor/1696166633-B90cmnnclj.png)
