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QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with IQ = 0.68 mA, and the transistor parameters are: Kn = 0.33 mA/V2, Kp = 0.11 mA/V2, λn = 8 mV−1, λp = 15 mV−1, VTN = 1.11 V, and VTP = −1.11 V. (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. VSD1(V) Format : 2.425052706943 VSD2(V) Format : 5.373043205536 VDS3(V) Format : 4.4890649765977 VDS4(V) Format: 8.5370484648972 Ad Format : 89.670985595823 Figure P11.64

QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with IQ = 0.68 mA, and the transistor parameters are: Kn = 0.33 mA/V2, Kp = 0.11 mA/V2, λn = 8 mV−1, λp = 15 mV−1, VTN = 1.11 V, and VTP = −1.11 V. (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. VSD1(V) Format : 2.425052706943 VSD2(V) Format : 5.373043205536 VDS3(V) Format : 4.4890649765977 VDS4(V) Format: 8.5370484648972 Ad Format : 89.670985595823 Figure P11.64

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QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with I Q = 0.68 m A , and the transistor parameters are: K n = 0.33 m A / V 2 , K p = 0.11 m A / V 2 , λ n = 8 m V − 1 , λ p = 15 m V − 1 , V T N = 1.11 V , and V T P = − 1.11 V . (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. V S D 1 ( V ) ◻ Format : 2.425052706943 V S D 2 ( V ) ◻ Format : 5.373043205536 V D S 3 ( V ) ◻ Format : 4.4890649765977 V D S 4 ( V ) ◻ Format: 8.5370484648972 A d ◻ Format : 89.670985595823
Figure P11.64

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QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with IQ = 0.84 mA, and the transistor parameters are: Kn = 0.37 mA/V2, Kp = 0.12 mA/V2, λn = 8 mV−1, λp = 19 mV−1, VTN = 1.48 V, and VTP = −1.48 V. (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. VSD1 (V) Format : 4.7039047822905 VSD2 (V) Format : 8.3026036628505 VDS3 (V) Format : 2.3423479083074 VDS4 (V) Format :2.8658923084038 Ad Format :27.7556360535 Figure P11.64
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