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Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which Vtp = −0.4 V, kp = 100 μA/V2, and W/L = 50. Channel length modulation can be neglected. a. For an input common mode voltage VCM within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V. c. What is the input differential voltage (vG1 − vG2) that steers the bias current entirely into Q1 ?

Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which Vtp = −0.4 V, kp = 100 μA/V2, and W/L = 50. Channel length modulation can be neglected. a. For an input common mode voltage VCM within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V. c. What is the input differential voltage (vG1 − vG2) that steers the bias current entirely into Q1 ?

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Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which V t p = − 0.4 V , k p = 100 μ A / V 2 , and W / L = 50 . Channel length modulation can be neglected. a. For an input common mode voltage V C M within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V . c. What is the input differential voltage ( v G 1 − v G 2 ) that steers the bias current entirely into Q 1 ?

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Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which Vtp = −0.4 V, kp′ = 100 μA/V2, and W/L = 50. Channel length modulation can be neglected. a. For an input common mode voltage VCM within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V. c. What is the input differential voltage (vG1 − vG2) that steers the bias current entirely into Q1?
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For an NMOS differential pair with a common-mode voltage VCM applied, as shown in Fig. 9.2, let VDD = VSS = 1.0 V, kn' = 0.4 mA/V^2, (W/L) 1,2 = 10, Vtn = 0.4 V, I = 0.16 mA, RD = 5kohm, and neglect channel-length modulation. (a) Find VOV and V GS for each transistor. (b) For V CM =0, find VS, ID1, ID2, VD1, VD2, and VO. (c) Repeat (b) for VCM = +0.4 V. (d) Repeat (b) for VCM = -0.1 V (e) What is the highest value of VCM for which Q1 and Q2 remain in saturation? (f) If current source I requires a minimum voltage of 0.2 V to operate properly, what is the lowest value allowed for VS and hence for VCM (g) What is the input common-mode range?
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For the PMOS differential amplifier shown in Fig. P8.2 let Vtp=-0.8V and k'pW/L=4mA/V^2. Neglect channel-length modulation.
(a) For VG1 = VG2 = 0V, find Vov and VGS for each of Q1 and Q2. Also find Vs, VD1, and VD2.
(b) If the current source requires a minimum voltage of 0.5 V, find the input common-mode range.

For the PMOS differential amplifier shown in Fig. P8.2 let Vtp = -0.8 V and kp'W/L = 4 mA/V^2. Neglect channel-length modulation. (a) For VG1 = VG2 = 0V, find Vov and VGS for each of Q1 and Q2. Also find Vs, VD1, and VD2. (b) If the current source requires a minimum voltage of 0.5 V, find the input common-mode range.

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