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Question 8. [10 marks] Design a CMOS amplifier using the configuration shown to give an input resistance of 1 MΩ and a voltage gain of at least vOUT/vIN = −5 V/V to a load resistance of 10 kΩ. Let VDD = 5 V, k′W/L = 0.5 mA/V2, |Vt| = 1, and VA = 50 V for all transistors, and assume that C → ∞. Give −VSS and R to provide the required gain. R : 5 kΩ −VSS: VSS = −3 V Figure 4: Common source amplifier.

Question 8. [10 marks] Design a CMOS amplifier using the configuration shown to give an input resistance of 1 MΩ and a voltage gain of at least vOUT/vIN = −5 V/V to a load resistance of 10 kΩ. Let VDD = 5 V, k′W/L = 0.5 mA/V2, |Vt| = 1, and VA = 50 V for all transistors, and assume that C → ∞. Give −VSS and R to provide the required gain. R : 5 kΩ −VSS: VSS = −3 V Figure 4: Common source amplifier.

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Question 8. [10 marks] Design a CMOS amplifier using the configuration shown to give an input resistance of 1 M Ω and a voltage gain of at least v O U T / v I N = − 5 V / V to a load resistance of 10 k Ω . Let V D D = 5 V , k ′ W L = 0.5 m A / V 2 , | V l | = 1 , and V A = 50 V for all transistors, and assume that C → ∞ . Give − V S S and R to provide the required gain. R : 5 k Ω − V S S : V S S = − 3 V Figure 4: Common source amplifier.

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Figure 1 shows a single stage common source MOSFET amplifier circuit. We wish to design the circuit to meet the following design specifications: Load Resistance: RL = 100 KΩ Input Resistance: Ri > 200 KΩ Mid-band Gain: Gv = Vo/Vi = −50 ± 20% Supply Voltage: +15 Volts Circuit Capacitors: CG = 10μF; CS = 47μF; CD = 10μF Figure 1. Common Source MOSFET Amplifier Pre-lab: (a) Design the amplifier to meet the specifications above by choosing values for resistors R1, R2, RD and RS. Begin your design by choosing an appropriate value for the bias current ID. If ID ≈ 0.3 mA, assume VT ≈ 1.7 V, Kn ≈ 0.02 A/V2 and VA = 100 V(λ = 0.01 V−1). Find the small signal approximation of the input resistance Rin where Rin = R1∥R2 Find the small signal approximation of the output resistance Ro, where Ro is given as Ro = RD∥RL∥ro. The small signal mid-band gain of the amplifier is given by Gv = −gmRo where gm = 2knID = kn(VGS−VT) Once you choose ID the DC biasing of the transistor can be found using simple rules of thumb. The voltage VG should be approximately equal to VDD/3 > VT. For maximum symmetry, VD should be biased at the midpoint between VD(Max) and VD(Min). Clearly, the maximum VD is VDD and the minimum VD > VG−Vt. For example, if Vt = 1.7 V and VG = 1/3VDD = 5 V, then VD ≈ 9 V for maximum symmetry.

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