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Refer to the reference inverter shown below. a. A reference inverter has (W/L)n = 1.5, (W/L)p = 10. Design NMOS and PMOS network to implement, Y = AB + C(D + E) b. This logic gate drives a load capacitance of 2.5C, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 40%?

Refer to the reference inverter shown below. a. A reference inverter has (W/L)n = 1.5, (W/L)p = 10. Design NMOS and PMOS network to implement, Y = AB + C(D + E) b. This logic gate drives a load capacitance of 2.5C, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 40%?

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Refer to the reference inverter shown below. a. A reference inverter has (W/L)n = 1.5, (W/L)p = 10. Design NMOS and PMOS network to implement, Y = AB + C(D + E) b. This logic gate drives a load capacitance of 2.5C, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 40%?

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A reference inverter has (W/L)n = 1.5, (W/L) p = 10. Assuming a load capacitance is doubled, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 70%? (Hint: propagation delay is proportional to the RC time constant of the inverter).
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Vtn = 0.8 V, Vtp = -0.9 V, a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. = 250 a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below., a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. =120 a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. is given. The pull-down section of a CMOS logic circuit is shown below.

a) Find the logic expression for Z. What function does this circuit implement?

b) Draw the pull-up network that completes the CMOS logic circuit.

c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 müm/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. for the equivalent inverter.

d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit.

a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below.
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(i) Design a CMOS logic circuit to implement the function Y = AB + C¯. Find the minimum width for each transistor such that the delay is not worse than the reference inverter. Assume that for the basic inverter n = 2 and p = 4 and that technology used is L = 0.5 μm. ( 8 marks) (ii) Consider the circuit shown below. (a) Express Y as a function of A and B. (b) Redraw the circuit using CMOS Transmission gate switch. (c) Compare the performance of the Transmission Gate switch to the NMOS switch and PMOS switch. (6 marks) (iii) Mark the correct answer in the following. (6 marks)VIH is a) the maximum input voltage level to be considered as High. b) the maximum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the minimum input voltage level to be considered as Low. VIL is a) the maximum input voltage level to be considered as High. b) the minimum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the maximum input voltage level to be considered as Low. The noise margin in the Low state for a logical circuit with VIH = 2.2 V, VIL = 0.4 V, VOH = 4.0 V and VOL = 0.2 V is a) 0.2 V. b) 2.0 V c) 1.8 V. d) 3.6 V.

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