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Shown in Figure Q2 is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 μA, R = 2 kΩ, and all transistors sized (W/L) = 18 μm/0.2 μm and having the device parameters for the 0.18−μm CMOS process in Appendix I. Figure 3 a. With vo = 1 V, are all transistors in saturation mode? b. What is the maximum voltage that can appear at vo while still keeping all transistors in saturation mode? c. Assuming all transistors are in saturation mode, what is the small-signal output resistance seen looking into the drain of Q4?

Shown in Figure Q2 is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 μA, R = 2 kΩ, and all transistors sized (W/L) = 18 μm/0.2 μm and having the device parameters for the 0.18−μm CMOS process in Appendix I. Figure 3 a. With vo = 1 V, are all transistors in saturation mode? b. What is the maximum voltage that can appear at vo while still keeping all transistors in saturation mode? c. Assuming all transistors are in saturation mode, what is the small-signal output resistance seen looking into the drain of Q4?

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  1. Shown in Figure Q2 is a PMOS current mirror with V D D = 1.8 V , I bias = 150 μ A , R = 2 k Ω , and all transistors sized ( W / L ) = 18 μ m / 0.2 μ m and having the device parameters for the 0.18 − μ m CMOS process in Appendix I. Figure 3 a. With v o = 1 V , are all transistors in saturation mode? b. What is the maximum voltage that can appear at v o while still keeping all transistors in saturation mode? c. Assuming all transistors are in saturation mode, what is the small-signal output resistance seen looking into the drain of Q 4 ?

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