Shown is a positive latch built using transmission gates. Calculate th

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Shown is a positive latch built using transmission gates. Calculate the setup time, tsetup , and the propagation delay from the input D to the output Q, td−q. Use Cg = 2 fF/μm, Cd = 1 fF/μm and W = L = 2λ = 0.25 μm. Assume that equivalent resistance of NMOS transistor of width W is 13 kΩ and that equivalent resistance of PMOS transistor of width 2 W is 13 kΩ, that is use the following values for the transistor resistances: Rsq, n = 13 kΩ and Rsq, p = 26 kΩ.

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Shown is a positive latch built using transmission gates. Calculate the setup time, $t_{setup}$ , and the propagation delay from the input $D$ to the output $Q, t_{d - q}$ . Use $C_{g} = 2 f F / μ m, C_{d} = 1 f F / μ m$ and $W = L = 2 λ = 0.25 μ m$ . Assume that equivalent resistance of NMOS transistor of width $W$ is $13 k Ω$ and that equivalent resistance of PMOS transistor of width $2 W$ is $13 k Ω$ , that is use the following values for the transistor resistances: $R_{s q, n} = 13 k Ω$ and $R_{s q, p} = 26 k Ω$ .