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Size the gates in the schematic below using a fanout factor of 3. Assume the reference inverter has a pMOS transistor of width 2 and an nMOS transistor of width 1.

Size the gates in the schematic below using a fanout factor of 3. Assume the reference inverter has a pMOS transistor of width 2 and an nMOS transistor of width 1.

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  1. Size the gates in the schematic below using a fanout factor of 3 . Assume the reference inverter has a pMOS transistor of width 2 and an nMOS transistor of width 1.

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Problem 3: (Short Circuit Power Consumption) For the circuit in Figure 2, assume that the input Vin is a periodic square wave signal (called "clock") of frequency 200 MHz, and has a rising transition time (from 0−100% of VDD ) of 0.2 ns and a falling transition time (from 100−0% of VDD ) of 0.2 ns. For the inverter in the figure, find the short circuit power consumption. Use the procedural hints listed below. Procedural Hints:Calculate the short circuit duration, tsc. Short circuit currents occur when both nMOS and pMOS transistors are simultaneously ON. Use the rise/fall times given. Calculate the peak short circuit currents. For simplicity assume that Ipeak_sc_LH and Ipeak_sc_HL are equal, and calculate the latter only. To calculate Ipeak_sc_HL, , assume that the short circuit current for the H-to-L transition peaks when Vin = VDD/2 and Vout = 9 VDD /10 (this is an arbitrary choice assumed for this problem alone). Now calculate the pMOS transistor current - this will be Ipeak_sc_HL. . Question: Does the nMOS current equal the pMOS current? If not, how do you account for InMOS−IpMO ? Using your results from (1) and (2), calculate the short circuit power dissipation. Note: Assume that VDD = 1.0 Volts, (W/L)p = 3.5 /0.1, and (W/L)n = 2 /0.1. Transistor properties are given by the 90 nm model parameters handout posted on the class web-site. For the current calculation, use the transistor parameters (not the equivalent resistance parameters) and ignore channel length modulation. Assume that there is an 89 fF load on Out.

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(i) Design a CMOS logic circuit to implement the function Y = AB + C¯. Find the minimum width for each transistor such that the delay is not worse than the reference inverter. Assume that for the basic inverter n = 2 and p = 4 and that technology used is L = 0.5 μm. ( 8 marks) (ii) Consider the circuit shown below. (a) Express Y as a function of A and B. (b) Redraw the circuit using CMOS Transmission gate switch. (c) Compare the performance of the Transmission Gate switch to the NMOS switch and PMOS switch. (6 marks) (iii) Mark the correct answer in the following. (6 marks)VIH is a) the maximum input voltage level to be considered as High. b) the maximum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the minimum input voltage level to be considered as Low. VIL is a) the maximum input voltage level to be considered as High. b) the minimum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the maximum input voltage level to be considered as Low. The noise margin in the Low state for a logical circuit with VIH = 2.2 V, VIL = 0.4 V, VOH = 4.0 V and VOL = 0.2 V is a) 0.2 V. b) 2.0 V c) 1.8 V. d) 3.6 V.

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The diagram below shows the structure of an inverter circuit built using an NMOS transistor of size 3/2, and a pull up resistor RD = 1kohm. Assuming zero body-bias, find the region of operation of the transistor and iD for a. vI = VDD/2 (2 points ) b. vI = VDD/3 (2 points) Repeat the above question with RD = 100kohm. ( 3 points) Note: 2lambda = 0.18 um is a convention used to represent transistor dimensions in terms of the technology length lambda. This is different from channel length modulation parameter. Sizing is shown in the form of W/L and as a factor of transistor feature size i.e. 2lambda. Assume long-channel device.

The diagram below shows the structure of an inverter circuit built using an NMOS transistor of size 3/2, and a pull up resistor RD = 1kohm. Assuming zero body-bias, find the region of operation of the transistor and iD for a. vI = VDD/2 (2 points ) b. vI = VDD/3 (2 points) Repeat the above question with RD = 100kohm. ( 3 points) Note: 2lambda = 0.18 um is a convention used to represent transistor dimensions in terms of the technology length lambda. This is different from channel length modulation parameter. Sizing is shown in the form of W/L and as a factor of transistor feature size i.e. 2lambda. Assume long-channel device.

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