Question

Notify Me Bookmark

Size the transistors in each of those gates so that its pullup and pulldown times are approximate equal. Assume effective resistances for NMOS as Rn = 6.47 KΩ, for PMOS as Rp = 29.6 KΩ. The loading capacitance for the network is CL. Please show all the steps. Please consider the following two cases: (15 pt) (1) In the worst case (2) In the best case a) f = a′b′c′+d′ b) f = a′b′+c′d′ c) f = a′b+bc

Size the transistors in each of those gates so that its pullup and pulldown times are approximate equal. Assume effective resistances for NMOS as Rn = 6.47 KΩ, for PMOS as Rp = 29.6 KΩ. The loading capacitance for the network is CL. Please show all the steps. Please consider the following two cases: (15 pt) (1) In the worst case (2) In the best case a) f = a′b′c′+d′ b) f = a′b′+c′d′ c) f = a′b+bc

Image text
  1. Size the transistors in each of those gates so that its pullup and pulldown times are approximate equal. Assume effective resistances for NMOS as R n = 6.47 K Ω , for PMOS as R p = 29.6 K Ω . The loading capacitance for the network is C L . Please show all the steps. Please consider the following two cases: (15pt) (1) In the worst case (2) In the best case a) f = a ′ b ′ c ′ + d ′ b) f = a ′ b ′ + c ′ d ′ c) f = a ′ b + b c

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Please use the 180 nm process parameters shown at the end of homework for all the homework questions. For NMOS as Rn = 6.47 KΩ, for PMOS as Rp = 29.6 KΩ, and C1 = 0.89 fF)Design the static complementary gates (CMOS gates) for the following logic expressions using pull-up/pull-down networks. Use a truth table to show logical equivalence for converted expressions. Assume inverted variables are available, i. e., you do not have to add inverters for complementary variables. (10 pt) a) a+b b) ab c) (a+b)c d) (ab)′+(cd)
Solution
0 0

For the gate shown below, assume the equivalent resistance of NMOS and PMOS transistors are Rn = 10 kΩ and Rp = 20 kΩ, respectively, and an equal junction capacitance of 0.1 fF for W L = 1. Ignore channel length modulation, and any other capacitances, but do not ignore the internal node junction capacitances. a. (2) What function is implemented by this circuit? b. (2) Size the transistors for equal worst case pull-up and pull-down resistances. c. (6) Devise a stick diagram representing the circuit layout. d. (8) Find the input patterns that give the worst-case low-to-high propagation delay (tpLH), and find this delay. e. (8) Redo part d for the worst-case high-to-low propagation delay (tpHL) f. (6) Calculate the logical effort for each of the inputs, and the gate parasitic delay. g. (6) Estimate the activity factor, αY0→1, for the output F, if P(A = 1) = P(B = 1) = P(C = 1) = 1/2. What is the energy dissipated for 0→1 transition? Assume VDD = 1 V, and for this part only, a total capacitance of 1 fF at output only.
Solution
0 0

Draw the circuit diagram of a CMOS gate (showing all the transistors) which implements the logic function ((A + B + C) • D) + E b. (15pt) On the circuit diagram show the sizes of the NMOS and PMOS devices so that the network has approximately the same worst case tpHL and tpLH as an inverter (with an NMOS W = 5µm and PMOS W = 11µm.) which is driving an equal capacitance. Assume that self-capacitances are negligibly small compared to the load capacitance. Avoid increasing the area unnecessarily.
Solution
0 0