Question

Notify Me Bookmark

Size the transistors in the following circuit such that the worst-case pull-up and pull down drive strengths are the some as an inverter with PMOS width of 2 and NMOS width of 1 . Size of transistor A is given for both PUN and PDN.

Size the transistors in the following circuit such that the worst-case pull-up and pull down drive strengths are the some as an inverter with PMOS width of 2 and NMOS width of 1 . Size of transistor A is given for both PUN and PDN.

Image text
Size the transistors in the following circuit such that the worst-case pull-up and pull down drive strengths are the some as an inverter with PMOS width of 2 and NMOS width of 1 . Size of transistor A is given for both PUN and PDN.

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Login Sign Up

Similar/Related Questions

Consider Mirror Adder circuit below: (a) Size NMOS and PMOS devices in the circuit so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in an inverter. Assume that all the transistors in the circuit and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2 × WMIN. You can mention sizes in the figure itself. (b) How can you resize transistors from your solution in (a) to make the circuit faster? You are not allowed to increase the total area of your circuit.
Solution
0 0

a) Do the two circuits in Figure 1 implement the same logic function? Provide the Boolean expression for the circuits. b) What is the appropriate transistor sizing for the logic circuit to have similar to 1X inverter delay? Fill in the empty boxes. Assume PMOS D has width of 2, and INV1X has WPMOS:WNMOS of 2:1. c) Assume the transistors have been sized to give a worst case output resistance of 12 kohm in both pull-up and pull-down networks for the worst-case input patterns. What input patterns (A-D) give the lowest output resistance when the output is low? What is the value of that resistance? d) What input patterns (A-D) give the lowest output resistance when the output is high? What is the value of that resistance? e) Neglecting parasitics and assuming a load capacitance of 100 fF, calculate the best case tpLH and tpHL.
Solution
0 0

Problem 1: Consider the logic circuit below to the left: (a) What is the logic function implemented by the design below? (b) Size NMOS and PMOS devices in the circuit below so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in the inverter shown to the right. Assume that all the transistors in the circuit above and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2×WMN. (c) For the logic design, identify the transition for the worst case 'high to low' and 'low to high' delay considering that only one of the input (among A, B, C) switches. Compute RC delay for these transitions. Assume that the resistance of a minimum width width (WMIN), the junction capacitance is C at each source and drain ends. Ignore any external load capacitance for the circuit.

Solution
0 0