Size the transistors in the following NFET network. Timing constraint: t <= RnCL. un/up = 2. Rn is the resistance of a 1X NFET. Try to minimize the total TR width heuristically.
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Size the transistors in the following NFET network. Timing constraint: t <= RnCL. un/up = 2. Rn is the resistance of a 1X NFET. Try to minimize the total TR width heuristically.