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Sketch a transistor-level schematic using static CMOS for the following function. You may assume you have both true and complementary versions of the inputs available (i.e. both A and A

Sketch a transistor-level schematic using static CMOS for the following function. You may assume you have both true and complementary versions of the inputs available (i.e. both A and A’). Simplify the logic functions if needed.

Sketch a transistor-level schematic using static CMOS for the following function. You may assume you have both true and complementary versions of the inputs available (i.e. both A and A

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Sketch a transistor-level schematic using static CMOS for the following function. You may assume you have both true and complementary versions of the inputs available (i.e. both A and A

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Q1. A) Sketch a static CMOS gate computing the following equation. You may assume you have both true and complementary versions of the inputs available. Y = (B⋅(A+C)+D)⋅(A+D)¯ B) Design the size of transistors in a way that tpdr = tpdf . Explain the different steps that you took to reach the final answer. Wmin = 200 nm L = 60 nm μn = 2μp VDD = 1.0 V C) First, convert the circuit to its RC model. Then, estimate tpd of the designed circuit using the Elmore delay model. Suppose that a unit transistor has R = 10 k and C = 0.1 fF and your circuit is deriving a 20 FF capacitance (a 20 fF capacitor is connected to the output).
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A full-adder is a basic combinational block used to build complex digital circuits. It is basically a 1-bit adder, that computes the sum S and output carry Cout of two input bits, A and B, plus the initial input carry Cin. The truth table of the full-adder is shown below. Cin A B S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1. Derive the logic functions for S and Cout. Use only AND, OR, and negation operators in your expressions. You can use whatever method you like (boolean algebra, Karnaugh maps, etc.). 2. Implement both of the functions as static CMOS logic gates (at most followed by an inverter). Draw the transistor-level schematics. You can assume that both the direct and negated versions of each input are available. 3. Size all the devices in the pull-up (PU) networks of your gates, so that the equivalent resistance of each PU is the same as that of a PMOS with W/L = 2. Repeat for the pull-down (PD) networks and a reference NMOS with W/L = 1. When you size a transistor network, you should always consider the input logic values that yield the worst-case equivalent resistance. Neglect the effect of internal node capacitances.
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Pass Transistor Logic VDD = 2.5 V(W/L)2 = 1.5 um/0.25 um (W/L)1 = 0.5 um/0.25 um (W/L)ni = 0.5 um/0.25 um kn′ = 115 uA/V2, kp′ = −30 uA/V2 VtN = 0.43 V, VtP = −0.4 V Figure 6.12 Level restoring circuit. Consider the circuit of Figure 6.12 . Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. a. What is the logic function performed by this circuit? b. Explain why this circuit has non-zero static dissipation. c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. d. Implement the same circuit using transmission gates. e. Replace the pass-transistor network in Figure 6.12 with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A, B and C.

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