Question

Notify Me Bookmark

Sometimes it is useful to have a logic circuit which has a two different thresholds for turning on and off the circuit depending on the state of the output (and in turn the input). This circuit goes by the name Schmitt trigger and an NMOS version is shown in figure 4. Determine for what voltage level at A will the circuit output a logic high when A swings from 0 V to VDD. What is the voltage at A for which the circuit will output a logic low if A swings from VDD to 0 V? Assume the ON resistance of all the N-MOSFETs are Ron and the threshold voltage of the MOSFETs are VTN. Figure 4: Schmitt Inverter

Sometimes it is useful to have a logic circuit which has a two different thresholds for turning on and off the circuit depending on the state of the output (and in turn the input). This circuit goes by the name Schmitt trigger and an NMOS version is shown in figure 4. Determine for what voltage level at A will the circuit output a logic high when A swings from 0 V to VDD. What is the voltage at A for which the circuit will output a logic low if A swings from VDD to 0 V? Assume the ON resistance of all the N-MOSFETs are Ron and the threshold voltage of the MOSFETs are VTN. Figure 4: Schmitt Inverter

Image text
Sometimes it is useful to have a logic circuit which has a two different thresholds for turning on and off the circuit depending on the state of the output (and in turn the input). This circuit goes by the name Schmitt trigger and an NMOS version is shown in figure 4. Determine for what voltage level at A will the circuit output a logic high when A swings from 0 V to VDD. What is the voltage at A for which the circuit will output a logic low if A swings from VDD to 0 V? Assume the ON resistance of all the N-MOSFETs are Ron and the threshold voltage of the MOSFETs are VTN. Figure 4: Schmitt Inverter

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?

Solution
0 0

The circuit shown in Figure 5-1 is a CMOS logic gate of some type. NOTE: Alternative symbols! a) Fill in the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] If 0 V represents a logic low, and +5 V represents a logic high, what is the logic gate function of this circuit? [2] c) Determine the output resistance ROUT of the CMOS gate of Figure 5-1 for each combination of inputs. [8] NOTE: ROUT is the Thevenin Resistance of the Gate. It is the total resistance connected between VDD and the output OR between the output and GROUND, depending on the state of the MOSFET switches. GIVEN : rDSn = 190 ohm and rDSp = 350 ohm d) If this gate exhibits a worst-case Low-to-High (tpLH) propagation delay of 60nsec when driving a given capacitive load, what would you expect the worst-case High-to-Low (tpHL) propagation delay to be?

The circuit shown in Figure 5-1 is a CMOS logic gate of some type. NOTE: Alternative symbols! a) Fill in the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] If 0 V represents a logic low, and +5 V represents a logic high, what is the logic gate function of this circuit? [2] c) Determine the output resistance ROUT of the CMOS gate of Figure 5-1 for each combination of inputs. [8] NOTE: ROUT is the Thevenin Resistance of the Gate. It is the total resistance connected between VDD and the output OR between the output and GROUND, depending on the state of the MOSFET switches. GIVEN : rDSn = 190 ohm and rDSp = 350 ohm d) If this gate exhibits a worst-case Low-to-High (tpLH) propagation delay of 60nsec when driving a given capacitive load, what would you expect the worst-case High-to-Low (tpHL) propagation delay to be?
Solution
1 0

P R O B LEM II. 6 a) Express F¯ in a simplified sum-of-products form given that F = AB¯+CD¯. b) Implement the logic function F = AB¯+CD¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds VIL = VOL = VL and VIH = VOH = VH, respectively. Assume the supply voltage is VS, and that the on-state resistance of the NMOS transistors is RON. Determine the lowest value of the pull-up resistor RPU for which the circuit will obey the static discipline in terms of RON, VS, VL, and VH; not all variables need appear in your answer. c) Implement the logic function F = AB¯+CD¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a). ) d) Suppose that the NMOS and CMOS circuits above drive a capacitance CL. Assume that the on-state resistance of both the PMOS and NMOS transistors is RON. For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to VH. Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1, C = 0, and D = 1, and that a 0−V to 5−V square-wave signal is applied to the input A. Assume the square wave cycle time is T, and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance CL load.
Solution
0 0