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Static CMOS logical family always realize inverted logical functions such as NAND, NOR or A(B+C)¯. This is because Both nMOS and pMOS pass logical 0 and logical 1 voltages levels, respectively, well. nMOS transistors are well-isolate pMOS are good passers of logical 1 pMOS transistors have higher resistance There is a pMOS pull-up (producing the logical 1 output) network, whose transistors that are turned ON with 0 logical input. Also, because there is an nMOS pull-down (producing logical 0 output) network, whose transistors are turned ON with logical 1 inputs.

Static CMOS logical family always realize inverted logical functions such as NAND, NOR or A(B+C)¯. This is because Both nMOS and pMOS pass logical 0 and logical 1 voltages levels, respectively, well. nMOS transistors are well-isolate pMOS are good passers of logical 1 pMOS transistors have higher resistance There is a pMOS pull-up (producing the logical 1 output) network, whose transistors that are turned ON with 0 logical input. Also, because there is an nMOS pull-down (producing logical 0 output) network, whose transistors are turned ON with logical 1 inputs.

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Static CMOS logical family always realize inverted logical functions such as NAND, NOR or A ( B + C ) ¯ . This is because Both nMOS and pMOS pass logical 0 and logical 1 voltages levels, respectively, well. nMOS transistors are well-isolate pMOS are good passers of logical 1 pMOS transistors have higher resistance There is a pMOS pull-up (producing the logical 1 output) network, whose transistors that are turned O N with 0 logical input. Also, because there is an nMOS pull-down (producing logical 0 output) network, whose transistors are turned ON with logical 1 inputs.

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Consider the CMOS complex gate in the figure, whose pMOS network is shown as a box. a) Express the realized logic function and then draw the complete circuit, by drawing the pMOS transistors as well (Redraw nMOS transistors as they are, because you will need them in (b) and (c)) b) Assign each transistor its relative size, such that charging and discharging resistors (corresponding to propagation delays) are same as those of a unit inverter (Assume μn ≈ 2μp ). c) Determine and indicate parasitic capacitances at each relevant node, in terms of unit capacitance C (Consider drain/source capacitance halving only for merged+uncontacted diffusions). Then, express the rising and falling propagation delays ( tpLH and tpHL ) in terms of R and C (Use 0.69 factor as well and include Elmore delays). d) Assume that, as a designer, you feel that the pull-down delay can be improved if the positions of A−D and C-B nMOSTs are replaced (C-B close to the output; A-D close to the ground). Redraw the circuit for this new placing (only nMOSTs are replaced), indicate the relevant parasitic node capacitances and re-calculate tpHL to see if there is an improvement. It will be better if you add your comments as well.
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Fill in the truth table for the circuit above. It's easy to do. When the input to an NMOS transistor is 1 , the transistor turns on. Therefore, in the circuit above, when C is a 1, the output, F, will be zero. Now you can fill that in on the truth table; whenever C is a 1, F will be 0 . You should also see that when A is 1 and B is 0, the output, F, will be 0, because both series NMOS transistors are on. The PMOS transistor are in the pull-up network. They turn on when their input is 0. If you carefully check every input case, you will see the when the pull-up network is on, the pull-down network is off, and vice-versa. That is a requirement for proper CMOS design. Use the reasoning described above to complete the entire truth table.
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