Question

Notify Me Bookmark

The above logic circuit is composed of two cascaded MOSFET circuits. The circuit has inputs A and B, and output C. A) Which logic gate (NOT, AND, NAND, OR, NOR, XOR) best describes the function between inputs A and B and output C in the above circuit? Select only one logic gate. B) Based on the above MOSFET circuit, if inputs A = 1 and B = 1, what is output C?

The above logic circuit is composed of two cascaded MOSFET circuits. The circuit has inputs A and B, and output C. A) Which logic gate (NOT, AND, NAND, OR, NOR, XOR) best describes the function between inputs A and B and output C in the above circuit? Select only one logic gate. B) Based on the above MOSFET circuit, if inputs A = 1 and B = 1, what is output C?

Image text
The above logic circuit is composed of two cascaded MOSFET circuits. The circuit has inputs A and B, and output C. A) Which logic gate (NOT, AND, NAND, OR, NOR, XOR) best describes the function between inputs A and B and output C in the above circuit? Select only one logic gate. B) Based on the above MOSFET circuit, if inputs A = 1 and B = 1, what is output C?

Detailed Answer

1 0

Please enter your email here. You will get email when this question is answered by our tutor.

Answer
Doubtrix Logo

This Problem has been solved!

You'll get a detailed, step-by-step and expert verified solution.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Login Sign Up
  • Student Reviews:
  • (1)
  • Correct answers (1)
  • Complete solution (1)
  • Step-by-step solution (1)
  • Fully explained (1)

Similar/Related Questions

A full-adder is a basic combinational block used to build complex digital circuits. It is basically a 1-bit adder, that computes the sum S and output carry Cout of two input bits, A and B, plus the initial input carry Cin. The truth table of the full-adder is shown below. Cin A B S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1. Derive the logic functions for S and Cout. Use only AND, OR, and negation operators in your expressions. You can use whatever method you like (boolean algebra, Karnaugh maps, etc.). 2. Implement both of the functions as static CMOS logic gates (at most followed by an inverter). Draw the transistor-level schematics. You can assume that both the direct and negated versions of each input are available. 3. Size all the devices in the pull-up (PU) networks of your gates, so that the equivalent resistance of each PU is the same as that of a PMOS with W/L = 2. Repeat for the pull-down (PD) networks and a reference NMOS with W/L = 1. When you size a transistor network, you should always consider the input logic values that yield the worst-case equivalent resistance. Neglect the effect of internal node capacitances.
Solution
0 0

Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?

Solution
0 0

In the dynamic logic circuit shown below, all the transistors have the minimum channel length, and their sizes (widths) are marked. The inverter at the output is a standard static CMOS inverter with a PMOS size of 2 and an NMOS size of 1 . For a unit-sized NMOS or PMOS transistor, the intrinsic capacitance at its drain or source terminal is CD, and the capacitance at its gate is CG. For unit-sized NMOS and PMOS transistors, their onresistances are RN and RP, respectively. CD = CG = 1 fF and RP = 2 RN = 2 kΩ. (a) Express y as a Boolean function of the inputs A, B, C and D in the evaluation phase (CLK = 1). (b) Find the capacitances at nodes y, a, b and c, respectively. (c) Let A = B = D = 1 and C = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase (CLK = 0). Estimate the time it takes for the voltage at y to decrease from VDD to VDD/2 in the evaluation phase. (d) Repeat (c) if nodes a, b and c are at VDD in the pre-charge phase. (e) If the inputs are C = 1 and A = B = D = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase. Considering the charge sharing effect, what is the voltage at node y in the evaluation phase? It is known VDD = 2.5 V, VTN = 0.5 V and the body effect of the transistors can be ignored.

Solution
0 0