The circuit of Fig. 4 must be designed for a voltage drop of 100 mV ac

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The circuit of Fig. 4 must be designed for a voltage drop of 100 mV across Rs. Assume the impedance of a capacitor is negligible. Fig. 4 (a) Calculate the minimum allowable value of W/L if M1 must remain in saturation. (10 pt) (b) Based on W/L and VG value calculated in (a), what are the required values of R1 and R2 if the input impedance must be 100 kΩ? (10 pt) Apply for all problems Assume μnCox = 200 μA V2, μpCox = 100 μA V2, VTH = 0.5 for NMOS and −0.5 V for PMOS, λn = λp = 0.01. ro = 1 λID

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Apply for all problems Assume

μ_{n} C_{o x} = 200 \frac{μ A}{V^{2}}, μ_{p} C_{o x} = 100 \frac{μ A}{V^{2}}, V_{T H} = 0.5

for NMOS and

- 0.5 V

for

P M O S, λ_{n} = λ_{p} = 0.01

r_{o} = \frac{1}{λ I_{D}}

The circuit of Fig. 4 must be designed for a voltage drop of $100 m V$ across Rs. Assume the impedance of a capacitor is negligible. Fig. 4 (a) Calculate the minimum allowable value of $W / L$ if $M_{1}$ must remain in saturation. (10 pt) (b) Based on W/L and $V_{G}$ value calculated in (a), what are the required values of $R_{1}$ and $R_{2}$ if the input impedance must be $100 k Ω$ ? (10 pt)