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The circuit shown below shows a PMOS transistor operating as a switch. Knowing that the power supply VDD = 2.5 V ensures the High level, Vtp = -0.7 V, Kp = 200 uA/V^2, CL = 10pF, Determine: 1. The end value of VO when VI changes from Low to High 2. The end value of VO when VI changes from High to Low. 3. The propagation delay tpLH

The circuit shown below shows a PMOS transistor operating as a switch. Knowing that the power supply VDD = 2.5 V ensures the High level, Vtp = -0.7 V, Kp = 200 uA/V^2, CL = 10pF, Determine: 1. The end value of VO when VI changes from Low to High 2. The end value of VO when VI changes from High to Low. 3. The propagation delay tpLH

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The circuit shown below shows a PMOS transistor operating as a switch. Knowing that the power supply VDD = 2.5 V ensures the High level, Vtp = -0.7 V, Kp = 200 uA/V^2, CL = 10pF, Determine: 1. The end value of VO when VI changes from Low to High 2. The end value of VO when VI changes from High to Low. 3. The propagation delay tpLH

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Similar/Related Questions

The circuit shown below shows a PMOS transistor operating as a switch in the ON position. (a) If initially vO= 0 and at t = 0, vI is raised to VDD, what is the final value VoH reached at the output? (b) If initially vO = VDD and at t = 0, vI is lowered to 0 V, what is the final value VOL reached at the output? (c) For the situation in (a), find tPLH for vO to rise from 0 to VDD/2. Let kp = 225 uA/V^2, VDD = 1.8 V, and |Vtp| = 0.5 V and C = 10 pF.
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Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
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The inverter circuit shown uses a device X with graphical characteristics consisting of two straight lines (see graph on right): one through the origin and the point (VA, IA), and the other a horizontal line at ix = IA, starting at vx = VA. The MOSFET parameters are: k = 1.6 mA/V2 and Vt = 0.7 V. The supply voltage is VDD = 4 V, and for device X, VA = 0.5 V. Find the value of VOH in V. a) 4.5 b) 3.5 c) 4.0 d) 5.0 e) 3.0 Find the value of VOL in V, when IA = 1 mA. a) 0.233 b) 0.168 c) 0.148 d) 0.195 e) 0.290 In the following three questions, assume that the value of IA is adjusted such that it results in VOL = 0.2 V. Hint: When the output is low, IA = 12 k(2(VOH − Vt)VOL − VOL2) 3. Find the average static power dissipation (in mW ) when the input is low 50% of the time, and high 50% of the time. a) 1.51 b) 1.06 c) 2.05 d) 3.36 e) 2.66 4. Find the value of VM in V (at vI = VM, vO = VM ). a) 1.64 b) 2.00 c) 1.83 d) 1.92 e) 1.74 5. Find the high-to-low propagation delay ( tPHL in ns ) when a 1 pF capacitor is connected between the output of the inverter and ground. Use the average capacitor current method. a) 0.249 b) 0.212 c) 0.185 d) 0.380 e) 0.301

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