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The figure below shows a S-R latch (Vdd = 2.5 v, L = 0.25 um, λ = 0, γ = 0, neglect short channel effects, (W/L)1,3 = 2, (W/L)2,4 = 8) (a) Find the minimum values of M5, M6, M7 and M8 that will allow the latch to switch states (b) Find the minimum width of the set or reset pulse to ensure proper operation. Assume CQ = 20 fF and Ca = 20 F (c) Modify the circuit above (show the drawing) such that it becomes a SRAM cell. Make sure to label all the devices as well as the relevant signal lines. Find the size for the access device for a write operation. (d) What is the static power dissipation of the memory cell in (c)?

The figure below shows a S-R latch (Vdd = 2.5 v, L = 0.25 um, λ = 0, γ = 0, neglect short channel effects, (W/L)1,3 = 2, (W/L)2,4 = 8) (a) Find the minimum values of M5, M6, M7 and M8 that will allow the latch to switch states (b) Find the minimum width of the set or reset pulse to ensure proper operation. Assume CQ = 20 fF and Ca = 20 F (c) Modify the circuit above (show the drawing) such that it becomes a SRAM cell. Make sure to label all the devices as well as the relevant signal lines. Find the size for the access device for a write operation. (d) What is the static power dissipation of the memory cell in (c)?

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  1. The figure below shows a S-R latch (Vdd=2.5v, L = 0.25 u m , λ = 0 , γ = 0 , neglect short channel effects, ( W / L ) 1 , 3 = 2 , ( W / L ) 2 , 4 = 8 ) (a) Find the minimum values of M5, M6, M7 and M8 that will allow the latch to switch states (b) Find the minimum width of the set or reset pulse to ensure proper operation. Assume C Q = 20 F F and C a = 20 F (c) Modify the circuit above (show the drawing) such that it becomes a SRAM cell. Make sure to label all the devices as well as the relevant signal lines. Find the size for the access device for a write operation. (d) What is the static power dissipation of the memory cell in (c)?

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