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The following figure shows a pseudo-NMOS inverter gate, in which gate-grounded PMOS acts like resistive load. Assume VDD = 2.0V, unCox = 100 uA/V2, upCox = 50 uA/V2, VTHN = 0.4V, VTHP = -0.4V, lambda_n = 0, and lambda_p = 0. When (W/L)n =10 and Vin = VDD, Vout = 0.2V. Determine (W/L)p. Also assume that both NMOS and PMOS operate in linear region although PMOS actually operates in saturation region.

The following figure shows a pseudo-NMOS inverter gate, in which gate-grounded PMOS acts like resistive load. Assume VDD = 2.0V, unCox = 100 uA/V2, upCox = 50 uA/V2, VTHN = 0.4V, VTHP = -0.4V, lambda_n = 0, and lambda_p = 0. When (W/L)n =10 and Vin = VDD, Vout = 0.2V. Determine (W/L)p. Also assume that both NMOS and PMOS operate in linear region although PMOS actually operates in saturation region.

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The following figure shows a pseudo-NMOS inverter gate, in which gate-grounded PMOS acts like resistive load. Assume VDD = 2.0V, unCox = 100 uA/V2, upCox = 50 uA/V2, VTHN = 0.4V, VTHP = -0.4V, lambda_n = 0, and lambda_p = 0. When (W/L)n =10 and Vin = VDD, Vout = 0.2V. Determine (W/L)p. Also assume that both NMOS and PMOS operate in linear region although PMOS actually operates in saturation region.

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The circuit shown in Figure 7 is supposed to work as an inverter where it has the following values for its parameters: VDD = 1.8V, lambda_1 = lambda_2 = 0, unCox = 100 uA/V2, upCox = 50 uA/V2, VTH,N=0.4V, VTH,P= -0.5V. (W/L)2 = 3/0.18 1. Assuming that vout,min = 0.1 V when vin = VDD, determine the mode of the transistors M1 and M2. 2. Using the previous results, determine the value of (W/L)1 that will guarantee that vout, min = 0.1 V, when vin = VDD.

The circuit shown in Figure 7 is supposed to work as an inverter where it has the following values for its parameters: VDD = 1.8V, lambda_1 = lambda_2 = 0, unCox = 100 uA/V2, upCox = 50 uA/V2, VTH,N=0.4V, VTH,P= -0.5V. (W/L)2 = 3/0.18 1. Assuming that vout,min = 0.1 V when vin = VDD, determine the mode of the transistors M1 and M2. 2. Using the previous results, determine the value of (W/L)1 that will guarantee that vout, min = 0.1 V, when vin = VDD.

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For the amplifier below, following design information is provided: VDD = 3.3 V, R = 2.4 kΩ, ISS = 1.8 mA, k1 = k2 = 5 mA/V2, VTH,1 = VTH,2 = 0.5 V, λ = 0.1 V−1, γ = 0, ki′ = μ0Cox, ki = μ0 Cox(W L)i. Assume that both transistors are identical and in the saturation region. Finally, NMOS and PMOS bulk terminals are connected to the ground and VDD, respectively. a) What is the DC bias voltage for M1 and M2 given that the voltage drop across ISS is 0.4 V ? You can neglect the channel length modulation, here. Check that the transistors are in the correct operation-mode. b) The resistors will be realized using identical PMOS transistors M3 and M4. If the transistors to be used will have k3 = k4 = 1.5 mA/V2, what will be their overdrive voltages? Check that the transistors are in the correct operation-mode. c) What is the differential voltage gain AV,diff = Vout/Vid in dB ? d) ISS will be realized as a cascode current source. Assume that the voltage drop of 0.4 V is equally shared by the two transistors, M5 and M6 having k5′ = k6′ = 0.5 mA/V2 and VTH, 5 = VTH, 6 = 0.5 V. Assuming the gate voltages of both transistors are 1 V, find the W/L ratios of each device. Once again, you can neglect the channel length modulation here. e) Considering (d), how would the W/L ratios qualitatively change (increase/decrease/stays the same), if γ > 0 ? Explain your reasoning analytically, i. e. , using appropriate equations. f) Using the cascode current source, calculate the common-mode gain of the circuit AV, CM = Vout /Vin in dB, where Vin . s applied to the gates of both M1 and M2. Assume λ = 0.1 V−1 for M5 and M6. g) Calculate the CMRR of the circuit in dB.
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For the circuit shown in Figure 2, VDD = 5 V, and transistors M1 and M2 have properties µnCox = 200µA/V2, (W/L) = 10, Vt0 = 0.7 V, and λ = 0. You may neglect the body effect below, unless you are specifically asked to consider it. Figure 2. Circuit for Problem 2. a) Draw the circuit above, and label the drain, gate, source, and bulk nodes for both transistors, using labels VD1, VG1, VS1, and VB1 for the drain, gate, source, and bulk nodes of device M1, respectively, and similarly for M2. In total, there should be 8 labels in your schematic. For this part, assume the transistors are in saturation. b) Determine the valid input range for the circuit under consideration; that is, determine the range on the input voltage Vin such that transistors M1 and M2 are operating in the saturation region. Note that, in your analysis, you are not constrained to Vin values between 0 V and VDD, inclusive; e.g., if Vin = 100 V keeps both of the transistors in saturation, then Vin = 100 V should be included in your range of valid input voltages. Your answer to this part should take the form Vin,low ≤ Vin ≤ Vin,high ; hopefully, it is obvious that you are being asked to provide numerical answers for the lower- and upper-bounds Vin,low and Vin,high , respectively. c) For the valid input range that you determined in part (b), determine the corresponding output voltage range; that is, determine Vout,low ≤ Vout ≤ Vout,high when the input is constrained to Vin,low ≤ Vin ≤ Vin,high. . As before, you should report numerical values for the lower- and upper-bounds Vout,low and Vout,high, , respectively. d) Determine the "on voltage" VON2 (or, as in the Sedra/Smith textbook, the "overdrive voltage") and drain current ID2 of transistor M2 over the range of valid input voltages. Also, determine the drain current ID1 of M1 over the valid input range. e) If you were to consider it, would any of the transistors in the circuit above be affected by the body effect? If "yes," then list the device (or, devices, as the case may be). Qualitatively speaking, how would your answers to parts (b) and (c) change if you were to take the body effect into account? Explain your reasoning.
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